Digital Signal Processor,Military Known Good Die - SMJ320C30KGD


Digital Signal Processor,Military Known Good Die



The SMJ320C30KGDB digital signal processor (DSP) is a high-performance, 32-bit floating-point processor manufactured in 0.72-µm, double-level metal CMOS technology.

The SMJ320C30KGDB internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SMJ320C30KGDB optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The SMJ320C30KGDB can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/ O, and a short machine-cycle time. High performance and ease of use are results of these features.

The large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple interrupt structure enhanced general-purpose applications. The SMJ320C30KGDB supports a wide variety of system applications from host processor to dedicated coprocessor.

High-level language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.


  • Military Operating Temperature Range -55°C to 125°C, QML Processing
  • Fast Instruction Cycle Time of 50 ns and 40 ns
  • Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
  • 32-Bit Instruction and Data Words, 24-Bit Addresses
  • Integer, Floating-Point, and Logical Operations
  • 40- or 32-Bit Floating-Point/ Integer Multiplier and Arithmetic Logic Unit (ALU)
  • 24 × 24-Bit Integer Multiplier, 32-Bit Product
  • 32 × 32-Bit Floating-Point Multiplier, 40-Bit Product
  • Parallel ALU and Multiplier Execution in a Single Cycle
  • 32-Bit Barrel Shifter
  • Eight Extended-Precision Registers (Accumulators)
  • Circular and Bit-Reversed Addressing Capabilities
  • Two Independent Bidirectional Serial Ports With Support for 8-, 16-, 24 -, or 32-Bit Transfers
  • Two 32-Bit Timers With Control and Counter Registers
  • Validated Ada Compiler
  • 64-Word × 32-Bit Instruction Cache
  • On-Chip Direct Memory Access (DMA) Controller for Concurrent I/ O and CPU Operation
  • One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block
  • Two 32-Bit External Ports (24- and 13-Bit Addresses)
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Zero-Overhead Loops With Single-Cycle Branches
  • Interlocked Instructions for Multiprocessing Support
  • Two- and Three-Operand Instructions
  • Conditional Calls and Returns
  • Block-Repeat Capability
  • Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments

EPIC is a trademark of Texas Instruments Incorporated.

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