Floating-Point Digital Signal Processors, Military Known Good Die - SMJ320C40KGDC

SMJ320C40KGDC (ACTIVE)

Floating-Point Digital Signal Processors, Military Known Good Die

 

Description

The TMP/ SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-um, double-level metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world\x92s first DSP designed for parallel processing. The on-chip parallel processing capabilities of the \x92C40 make the floating-point performance required by many applications achievable and cost-effective.

The TMP/ SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor communication using simple communication software with no external hardware. This allows connectivity with no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA coprocessor is able to handle the CPU I/O requirements.

The features of the communication ports are:

  • Six communication ports for direct interprocessor communication and processor I/O
  • 20 MBps bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface
  • Separate input and output first-in, first-out (FIFO) buffers for I/ O and processor-to-processor communication
  • Automatic arbitration and handshaking for direct processor-to-processor connection

The DMA coprocessor allows concurrent I/O and CPU processing for superior sustained CPU performance.
The key features of the DMA coprocessor:

  • Link pointers that allow DMA channels to auto-initialize
  • Parallel CPU operation and DMA transfers
  • Six DMA channels support communication-port-to-memory data transfers

The TMP/SMJ320C40KGD CPU is configured for high-speed internal parallel processing. The key features of the CPU are:

  • Eight operations/ cycles
    • 40-/ 32-bit floating-point / integer multiply
    • 40-/32-bit floating-point/ integer arithmetic and logic unit (ALU) operation
    • Two data accesses
    • Two address-register updates
  • IEEE floating-point conversion
  • Division and square-root support
  • \x92C30 assembly language compatibility
  • Byte and halfword accessibility

Key factors in a parallel-processing implementation are the development tools that are available. The \x92C40 is supported by a host of parallel-processing development tools for developing and simulating code and for debugging parallel-processing systems. The code generation tools include:

  • Optimizing ANSI C compiler with a runtime library that supports use of communication ports and DMA
  • SPOX™, by Spectron Microsystems Incorporated, which provides parallel processing support as well as DMA and communication port drivers
  • Assembler and linker with support for mapping program and data to parallel processors.

The simulation tools include:

  • Parallel DSP system-level simulation, by Logic Modeling Corporation (LMC), which includes a hardware verification (HV) model and a full functional (FF) model
  • TI software simulator with high-level language debugger interface for simulating a single processor

The hardware development and verification tools include:

  • Parallel processor in-circuit emulator and high-level language debugger: XDS510™
  • Parallel processor development system with four TMS320C40s, local and global memory, and communication port connections

For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.

Features

  • SMJ: QML Processing to MIL-PRF-38535
  • TMP: Commercial Level Processing
  • Operating Temperature Ranges:
    • Military (M) -55°C to 125°C
    • Commercial (C) -25°C to 85°C
    • Commercial (L) 0°C to 70°C
  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • 'C40-50:
      • 40-ns Instruction Cycle Time:
        50 MFLOPS, 25 MIPS, 275 MOPS, 320 MBps
    • 'C40-40:
      • 50-ns Instruction Cycle Time:
        40 MFLOPS, 20 MIPS, 220 MOPS, 256 MBps
  • Six Communications Ports
  • 6-Channel Direct Memory Access (DMA) Coprocessor
  • Single-Cycle Conversion to and From IEEE-745 Floating-Point Format
  • Single Cycle 1/x, 1/x
  • Source-Code Compatible With SMJ320C30
  • Validated Ada Compiler
  • Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
  • 12 40-Bit Registers, 8 Auxiliary Registers, 14 Control Registers, and 2 Timers
  • IEEE Standard 1149.1 Test-Access Port (JTAG)
  • Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
    • High Port-Data Rate of 100 MBytes/s (Each Bus)
    • 16G-Byte Continuous Program/Data/Peripheral Address Space
    • Memory-Access Request for Fast, Intelligent Bus Arbitration
    • Separate Address-, Data-, and Control-Enable Pins
    • Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
  • Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments (TI™)
  • Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
  • On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
    • 512-Byte Instruction Cache
    • 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
    • ROM-Based Bootloader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories Over Any One of the Communications Ports

IEEE Standard 1149.1\x961990 Standard Test-Access Port and Boundary-Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
SPOX is a trademark of Spectron Microsystems, Inc.
XDS510 is a trademark of Texas Instruments Incorporated.

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