SMJ320F240 (NRND)

Fixed Point Digital Signal Processor, Military

Description

The SMJ320F240 is a member of a family of digital signal processor (DSP) controllers based on the TMS320C2xx generation of 16-bit fixed-point DSPs. This family is optimized for digital motor/motion control applications and contains 16K words of flash memory on chip. The DSP controller combines the enhanced TMS320 architectural design of the C2xLP core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications. These peripherals include the event manager module, which provides general-purpose timers and compare registers to generate up to 12 PWM outputs, and a dual 10-bit analog-to-digital converter (ADC), which can perform two simultaneous conversions within 6.1 µs.

The functional block diagram provides a high-level description of each component in the F240 DSP controller. The SMJ320F240 device is composed of three main functional units: a C2xx DSP core, internal memory, and peripherals. In addition to these three functional units, there are several system-level features of the F240 that are distributed. These system features include the memory map, device reset, interrupts, digital input/output (I /O), clock generation, and low-power operation.

Features

  • Processed to MIL-PRF-38535 (QML)
  • High-Performance Static CMOS Technology
  • Includes the T320C2xLP Core CPU
    • Object Compatible With the TMS320C2xx Family
    • Source Code Compatible With SMJ320C25
    • Upwardly Compatible With SMJ320C50
    • 50-ns Instruction Cycle Time
  • Memory
    • 544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM
    • 16K Words × 16 Bits of On-Chip Program Flash EEPROM
    • 224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Space)
  • Event-Manager Module
    • 12 Compare/Pulse-Width Modulation (PWM) Channels
    • Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Upand Up/Down Counting
    • Three 16-Bit Full-Compare Units With Deadband
    • Three 16-Bit Simple-Compare Units
    • Four Capture Units (Two With Quadrature Encoder-Pulse Interface Capability)
  • Dual 10-Bit Analog-to-Digital Conversion Module
  • 28 Individually Programmable, Multiplexed I/O Pins
  • Phase-Locked-Loop (PLL)-Based Clock Module
  • Watchdog Timer Module (With Real-Time Interrupt)
  • Serial Communications Interface (SCI) Module
  • Serial Peripheral Interface (SPI) Module
  • Six External Interrupts (Power Drive Protect, Reset, NMI, and Three Maskable Interrupts)
  • Four Power-Down Modes for Low-Power Operation
  • Scan-Based Emulation
  • Development Tools Available:
    • Texas Instruments (TI™) ANSI C Compiler, Assembler/Linker, and C-Source Debugger
    • Scan-Based Self-Emulation (XDS510™)
    • Third-Party Digital Motor Control and Fuzzy-Logic Development Support
  • –55°C to 125°C Operating Temperature Range, QML Processing
  • 132-Pin Ceramic Quad Flat Package (HFP Suffix)

TI and XDS510 are trademarks of Texas Instruments Incorporated.

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Other qualified versions of SMJ320F240

Version Part Number Definition
Catalog TMS320F240 TI's standard catalog product

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