The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs.
(1) Radiation tolerance is a typical value based upon initial device qualification. Radiation Data and Lot Acceptance Testing is available – contact factory for details.
(2) HardSIL™ technology and memory design under a license agreement with Silicon Space Technology (SST).
(3) SER calculated using CREME96 for geosynchronous orbit,
(4) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of 55°C to 125°C or operating life.
|Organization (Words by Bits)|
|Core Supply Voltage (Typ) (V)|
|I/O Supply Voltage 1 (Typ) (V)|
|512K x 32|
|Samples Not Available|