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SN54AC373-SP

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Octal D-type Transparent Latches With 3-State Outputs

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Data sheet

SN54AC373-SP

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family AC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Space
Number of channels 8 Technology family AC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Space
CFP (W) 20 90.5828 mm² 13.09 x 6.92
  • Operation of 2V to 6V VCC
  • Inputs accept voltages to 6V
  • Max tpd of 9.5ns at 5V
  • 3-state noninverting outputs drive bus lines directly
  • Full parallel access for loading
  • Operation of 2V to 6V VCC
  • Inputs accept voltages to 6V
  • Max tpd of 9.5ns at 5V
  • 3-state noninverting outputs drive bus lines directly
  • Full parallel access for loading

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
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Technical documentation

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Type Title Date
* Data sheet SNx4AC373 Octal D-type Transparent Latches with 3-State Outputs datasheet (Rev. F) PDF | HTML 28 Feb 2024
* SMD SN54AC373-SP SMD 5962-87555 08 Jul 2016
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 31 Aug 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 17 Nov 2022
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
Selection guide TI Space Products (Rev. I) 03 Mar 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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