Product details

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL Output type TTL Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Technology family ALS Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL Output type TTL Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Technology family ALS Rating Military Operating temperature range (°C) -55 to 125
LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Two-Way Asynchronous Communication Between Data Buses
  • pnp Inputs Reduce dc Loading
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

  • Two-Way Asynchronous Communication Between Data Buses
  • pnp Inputs Reduce dc Loading
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

These quadruple bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEBA and ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives the quadruple bus transceivers the capability to store data by simultaneously enabling OEBA and . Each output reinforces its input in this transceiver configuration. When both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (eight in all) retain their states. The 4-bit codes appearing on the two sets of buses are identical.

The SN54ALS243A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS243A is characterized for operation from 0°C to 70°C.

 

 

These quadruple bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEBA and ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives the quadruple bus transceivers the capability to store data by simultaneously enabling OEBA and . Each output reinforces its input in this transceiver configuration. When both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (eight in all) retain their states. The 4-bit codes appearing on the two sets of buses are identical.

The SN54ALS243A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS243A is characterized for operation from 0°C to 70°C.

 

 

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Type Title Date
* Data sheet Quadruple Bus Transceivers With 3-State Outputs datasheet (Rev. B) 01 Dec 1994
* SMD SN54ALS243A SMD 84013022A 21 Jun 2016
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Advanced Schottky (ALS and AS) Logic Families 01 Aug 1995

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