The SN65DSI84-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS or single-link LVDS with four data lanes per link.
The SN65DSI84-Q1 device is well suited for WUXGA (1920 × 1080) at 60 frames per second (fps) with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI84-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a 0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
|Serial Data Receiver Channels|
|Serial Data Transmitter Channels|
|Supply Voltage(s) (V)|
|PLL Frequency (MHz)|
|Operating Temperature Range (C)|
|Max Display Resolution|
|Max Input Data Rate (Mbps/lane)|
|Max Output Data Rate (Mbps/lane)|
|25 - 154||25 - 154||25MHz - 154MHz||25 - 154|
|-40 to 105||-40 to 105||-40 to 105||-40 to 85|
|MIPI D-Phy||MIPI D-Phy||DSI MIPI D-Phy||MIPI® DSI|
|1920 × 1200 60 fps at 24 bpp||1920 × 1200 60 fps at 24 bpp with reduced blanking||WQXGA 2560x1600 p60 @ 24bpp||4096 × 2304 60 fps at 18 bpp|
|Order Now||Order Now||Order Now||Order Now|
|Catalog||SN65DSI84||TI's standard catalog product|