Automotive Single Channel MIPI® DSI to Dual-Link LVDS Bridge - SN65DSI84-Q1

SN65DSI84-Q1 (ACTIVE)

Automotive Single Channel MIPI® DSI to Dual-Link LVDS Bridge

 

Description

The SN65DSI84-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS or single-link LVDS with four data lanes per link.

The SN65DSI84-Q1 device is well suited for WUXGA (1920 × 1080) at 60 frames per second (fps) with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

The SN65DSI84-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a 0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 3A
    • Device CDM ESD Classification Level C6
  • Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Single-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, and 60-fps 1366 × 768 Resolution at 18-bpp and 24-bpp
  • Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Single-Channel DSI to Dual-Link LVDS Operating Mode
  • LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8 V Main VCC Power Supply
  • Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package

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Parametrics Compare all products in CSI/DSI

 
Serial Data Receiver Channels
Serial Data Transmitter Channels
Supply Voltage(s) (V)
PLL Frequency (MHz)
Pin/Package
Operating Temperature Range (C)
Receiver Type
Max Display Resolution
Max Input Data Rate (Mbps/lane)
Max Output Data Rate (Mbps/lane)
Transmitter Type
SN65DSI84-Q1 SN65DSI83-Q1 SN65DSI85-Q1 SN65DSI86-Q1
4    4    8    2   
8    4    8    4   
1.8    1.8    1.8    1.2   
25 - 154    25 - 154    25MHz - 154MHz    25 - 154   
64HTQFP    64HTQFP    64HTQFP    64HTQFP   
-40 to 105    -40 to 105    -40 to 105    -40 to 85   
MIPI D-Phy    MIPI D-Phy    DSI MIPI D-Phy    MIPI® DSI   
1920 × 1200 60 fps at 24 bpp    1920 × 1200 60 fps at 24 bpp with reduced blanking    WQXGA 2560x1600 p60 @ 24bpp    4096 × 2304 60 fps at 18 bpp   
1000    1000    1000    1500   
1078    1078      5400   
LVDS    LVDS    LVDS    eDP 1.4   

Other qualified versions of SN65DSI84-Q1

Version Part Number Definition
Catalog SN65DSI84 TI's standard catalog product