The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a 0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
|Supply Voltage(s) (V)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|-40 to 105||-40 to 105||-40 to 105||-40 to 85|
|64HTQFP: 144 mm2: 12 x 12(HTQFP)||64HTQFP: 144 mm2: 12 x 12(HTQFP)||64HTQFP: 144 mm2: 12 x 12(HTQFP)||64HTQFP: 144 mm2: 12 x 12(HTQFP)|
|Order Now||Order Now||Order Now||Order Now|
|Catalog||SN65DSI85||TI's standard catalog product|