MIPI DSI Bridge to FlatLink LVDS - SN65DSI85


MIPI DSI Bridge to FlatLink LVDS


The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.

The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI85 is implemented in a small outline 5-mm × 5-mm PBGA at 0.5-mm pitch package, and operates across a temperature range from –40ºC to 85ºC.


  • Implements MIPI D-PHY Version 1.00.00
    Physical Layer Front-End and Display Serial
    Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One,
    Two, Three, or Four D-PHY Data Lanes Per
    Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets
    with RGB666 and RGB888 Formats
  • Suitable for 60 fps WQXGA 2560 × 1600
    Resolution at 18-bpp and 24-bpp Color, and
    WUXGA 1920 × 1200 Resolution with 3D
    Graphics at 60 fps (120 fps Equivalent)
  • MIPI® Front-End Configurable for Single-Channel
    or Dual-Channel DSI Configurations
  • FlatLink Output Configurable for Single-Link or
    Dual-Link LVDS
  • Supports Dual-Channel DSI ODD or EVEN and
    LEFT or RIGHT Operating Modes
  • Supports Two Single-Channel DSI to Two Single-
    Link LVDS Operating Mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz
    in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-
    Running Continuous D-PHY Clock or External
    Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low-Power Features Include SHUTDOWN Mode,
    Reduced LVDS Output Voltage Swing, Common
    Mode, and MIPI® Ultra-Low Power State (ULPS)
  • LVDS Channel SWAP, LVDS PIN Order Reverse
    Feature for Ease of PCB Routing
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-pin 5 mm × 5 mm BGA
  • Temperature Range: –40°C to 85°C

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Parametrics Compare all products in CSI/DSI

Serial Data Receiver Channels
Serial Data Transmitter Channels
Supply Voltage(s) (V)
PLL Frequency (MHz)
Approx. Price (US$)
Operating Temperature Range (C)
Receiver Type
Max Display Resolution
Max Input Data Rate (Mbps/lane)
Max Output Data Rate (Mbps/lane)
Transmitter Type
8     4     4    
8     4     8    
1.8     1.8     1.8    
50 - 154     50 - 154     50 - 154    
3.90 | 1ku     1.70 | 1ku     2.00 | 1ku    
-40 to 85     -40 to 85     -40 to 85    
MIPI D-Phy     MIPI D-Phy     MIPI D-Phy    
2560x1600p60 24bpp     1400x1050p60 24bpp     1920x1200p60 24bpp    
1000     1000     1000    
1078     1078     1078    
LVDS     LVDS     LVDS    

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