The SN65DSI85 DSI to FlatLink™ bridge features a dual-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.
The SN65DSI85 is well suited for WQXGA (2560x1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 x1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
Designed with industry compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI85 is implemented in a small outline 5x5mm PBGA at 0.5 mm pitch package, and operates across a temperature range from 40ºC to 85ºC.
|Serial Data Receiver Channels|
|Serial Data Transmitter Channels|
|Supply Voltage(s) (V)|
|PLL Frequency (MHz)|
|Approx. Price (US$)|
|Operating Temperature Range (C)|
|Max Display Resolution|
|Max Input Data Rate (Mbps/lane)|
|Max Output Data Rate (Mbps/lane)|
|50 - 154||50 - 154||50 - 154|
|64BGA MICROSTAR JUNIOR||64BGA MICROSTAR JUNIOR||64BGA MICROSTAR JUNIOR|
|3.90 | 1ku||1.70 | 1ku||2.00 | 1ku|
|-40 to 85||-40 to 85||-40 to 85|
|MIPI D-Phy||MIPI D-Phy||MIPI D-Phy|
|2560x1600p60 24bpp||1400x1050p60 24bpp||1920x1200p60 24bpp|
|Sample & Buy||Sample & Buy||Sample & Buy|