Home Interface HDMI, DisplayPort & MIPI ICs
Home
Interface
HDMI, DisplayPort & MIPI ICs

SN65DSI86

ACTIVE

Dual-channel MIPI® DSI to embedded DisplayPort™ (eDP ) bridge

Order now
Data sheet

SN65DSI86

ACTIVE
Data sheet Order now

Product details

Type Bridge Protocols MIPI DSI, eDP Rating Catalog Speed (max) (Gbps) 12 Supply voltage (V) 1.2 Operating temperature range (°C) -40 to 85
Type Bridge Protocols MIPI DSI, eDP Rating Catalog Speed (max) (Gbps) 12 Supply voltage (V) 1.2 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² 5 x 5
  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps 4K 4096 × 2304 resolution at 18 bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI front-end configurable for single-channel or dual-channel DSI configuration
  • Supports dual-channel DSI odd, even and left, right operating modes
  • 1.2-V main VCC power supply and 1.8-V supply for digital I/Os
  • Low-power features include panel refresh and MIPI ultralow power state (ULPS) support
  • DisplayPort lane polarity and assignment configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz frequencies through external reference clock (REFCLK)
  • ESD rating ±4 kV (HBM)
  • Packaged in 64ball 5-mm x 5-mm nFBGA (ZXH)
  • I2C configurable
  • Temperature range: –40°C to +85°C
  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps 4K 4096 × 2304 resolution at 18 bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI front-end configurable for single-channel or dual-channel DSI configuration
  • Supports dual-channel DSI odd, even and left, right operating modes
  • 1.2-V main VCC power supply and 1.8-V supply for digital I/Os
  • Low-power features include panel refresh and MIPI ultralow power state (ULPS) support
  • DisplayPort lane polarity and assignment configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz frequencies through external reference clock (REFCLK)
  • ESD rating ±4 kV (HBM)
  • Packaged in 64ball 5-mm x 5-mm nFBGA (ZXH)
  • I2C configurable
  • Temperature range: –40°C to +85°C

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
open-in-new Find other HDMI, DisplayPort & MIPI ICs
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Same functionality with different pin-out to the compared device
SN65DSI86-Q1 ACTIVE Automotive MIPI® DSI bridge to eDP Automotive grade with temperature range from –40°C to +85°C

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 4
Type Title Date
* Data sheet SN65DSI86 MIPI DSI to eDP Bridge datasheet (Rev. C) 01 Oct 2020
Application brief SN65DSI86 Programming Guide 17 Aug 2018
EVM User's guide SN65DSI86/SN65DSI96 EVM User’s Manual 21 Jun 2014
Application note SN65DSI86 and SN65DSI96 Hardware Implementation Guide 08 Oct 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SN65DSI86EVM — MIPI® DSI bridge to eDP evaluation module

The SN65DSI86EVM evaluation module (EVM) is a printed-circuit board (PCB) to help you evaluate the SN65DSI86 device for video applications with DSI and DisplayPort interface. This EVM can also be used as a hardware reference design for any implementation of the SN65DSI86.

User guide: PDF
Not available on TI.com
IDE, configuration, compiler or debugger

DSI-TUNER — Tuner video configuration software tool

The DSI Tuner video configuration tool generates the video timing and the configuration register values required to transfer the DSI data to the LVDS panel using the SN65DSI8x DSI-to-LVDS bridge device. The timing and the register values are calculated based on inputs entered in the input fields (...)
View options
Simulation model

SN65DSI86 IBIS Model

SLLM226.ZIP (92 KB) - IBIS Model
Download
Simulation model

SN65DSI86 IBIS Model (Rev. A)

SLLM226A.ZIP (92 KB) - IBIS Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
View options
Package Pins Download
NFBGA (ZXH) 64 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos