The SN65DSI86/96 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1.5Gbps per lane; a maximum input bandwidth of 12Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, or 5.4Gbps.
The SN65DSI86/96 is well suited for WQXGA at 60 frames per second, as well as 3D Graphics at 4K and True HD (1920x1080) resolutions at an equivalent 120fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
Integrated into the SN65DSI96 is an adaptive content management and backlight PWM control called Assertive Display®. The purpose of the Assertive Display® core is to optimize the viewing experience on a multimedia display as a function of viewing environment. It provides coherent management of the multimedia viewing experience from total darkness to bright ambient light conditions enabling the display to operate at reduced power and in bright sunshine.
|Serial Data Receiver Channels|
|Serial Data Transmitter Channels|
|Approx. Price (US$)|
|Operating Temperature Range (C)|
|Max Display Resolution|
|Max Output Data Rate (Mbps/lane)|
|64BGA MICROSTAR JUNIOR|
|5.61 | 1ku|
|-40 to 85|
|up to 4096x2304|
|Sample & Buy|
|Automotive||SN65DSI86-Q1||Q100 devices qualified for high-reliability automotive applications targeting zero defects|
|Part #||Name||Product Family||Comments|
|SN75DP130||DisplayPort Redriver Supporting RBR, HBR, and HBR2 (5.4Gbps)||Display & Imaging SerDes - DisplayPort||DisplayPort Redriver|
|HD3SS213||5.4Gbps DisplayPort 1.2a 2:1/1:2 Differential Switch||Display & Imaging SerDes - DisplayPort||DisplayPort 2:1/1:2 Switch|