The SN65DSI86 and SN65DSI96 (SN65DSIx6) DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.
The SN65DSIx6 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 \xD7 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
Integrated into the SN65DSI96 is an adaptive content management and backlight PWM control called Assertive Display®. The Assertive Display core optimizes the viewing experience on a multimedia display as a function of viewing environment. It provides coherent management of the multimedia viewing experience from total darkness to bright ambient light conditions enabling the display to operate at reduced power and in bright sunshine.
Designed with industry compliant interface technology, the SN65DSIx6 is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.
The SN65DSIx6 is implemented in a small outline, 5-mm × 5-mm, MicroStar Junior ball-grid array (BGA) at 0.5- mm pitch package, and operates across a temperature range from 40°C to +85°C.
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|Serial Data Transmitter Channels|
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|PLL Frequency (MHz)|
|Operating Temperature Range (C)|
|Max Display Resolution|
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|Automotive||SN65DSI86-Q1||Q100 devices qualified for high-reliability automotive applications targeting zero defects|