Dual-Channel MIPI® DSI to Embedded DisplayPort™  (eDP ) Bridge - SN65DSI86


Dual-Channel MIPI® DSI to Embedded DisplayPort™ (eDP ) Bridge



The SN65DSI86 and SN65DSI96 (SN65DSIx6) DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSIx6 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 \xD7 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

Integrated into the SN65DSI96 is an adaptive content management and backlight PWM control called Assertive Display®. The Assertive Display core optimizes the viewing experience on a multimedia display as a function of viewing environment. It provides coherent management of the multimedia viewing experience from total darkness to bright ambient light conditions enabling the display to operate at reduced power and in bright sunshine.

Designed with industry compliant interface technology, the SN65DSIx6 is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.

The SN65DSIx6 is implemented in a small outline, 5-mm × 5-mm, MicroStar Junior ball-grid array (BGA) at 0.5- mm pitch package, and operates across a temperature range from –40°C to +85°C.


  • Embedded DisplayPort™ (eDP™) 1.4 Compliant
    Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR),
    2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24
    Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI® D-PHY Version 1.1 Physical
    Layer Front-End and Display Serial Interface (DSI)
    Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One,
    Two, Three, or Four D-PHY Data Lanes Per
    Channel Operating up to 1.5 Gbps Per Lane
  • Supports 18 bpp and 24 bpp DSI Video Packets
    With RGB666 and RGB888 Formats
  • Suitable for 60 fps 4K 4096 × 2304 Resolution at
    18 bpp Color, and WUXGA 1920 × 1200
    Resolution with 3D Graphics at 60 fps (120 fps
  • MIPI Front-End Configurable for Single-Channel
    or Dual-Channel DSI Configuration
  • Supports Dual-Channel DSI Odd, Even and Left,
    Right Operating Modes
  • 1.2-V Main VCC Power Supply and 1.8-V Supply
    for Digital I/Os
  • Low-Power Features Include Panel Refresh and
    MIPI Ultralow Power State (ULPS) Support
  • DisplayPort Lane Polarity and Assignment
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz,
    and 38.4-MHz Frequencies Through External
    Reference Clock (REFCLK)
  • Adaptive Content Management and Backlight
    PWM Control Enabling Optimal User Viewing
    Experience in Both Low and Bright Ambient Light
    Environments Available in SN65DSI96.
  • Packaged in 64-Pin 5-mm x 5-mm MicroStar
    Junior BGA (ZQE)
  • Temperature Range: –40°C to +85°C

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Parametrics Compare all products in CSI/DSI

Serial Data Receiver Channels
Serial Data Transmitter Channels
Supply Voltage(s) (V)
PLL Frequency (MHz)
Operating Temperature Range (C)
Receiver Type
Max Display Resolution
Max Input Data Rate (Mbps/lane)
Max Output Data Rate (Mbps/lane)
Transmitter Type
SN65DSI86 SN65DSI86-Q1
2    2   
4    4   
1.2    1.2   
25 - 154    25 - 154   
-40 to 85    -40 to 85   
4096 × 2304 60 fps at 18 bpp    4096 × 2304 60 fps at 18 bpp   
1500    1500   
5400    5400   
eDP 1.4    eDP 1.4   

Other qualified versions of SN65DSI86

Version Part Number Definition
Automotive SN65DSI86-Q1 Q100 devices qualified for high-reliability automotive applications targeting zero defects

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