High Definition Image Sensor Receiver - SN65LVDS324


High Definition Image Sensor Receiver


TI IPCamera Modules using the SN65LVDS324 Available Through Leopard Imaging Inc

Aptina AR0331

The Aptina AR0331Camera Module with TI's SN65LVDS324 and IPCamera DM385 with 1.8V I/O interface. Streams 1080p@60fps H.264 video.
- $150.00

Panasonic MN34041

The Panasonic MN34041Camera Module with TI's SN65LVDS324 and TI IPCamera on Leopardboard 36x. It can stream 1080p@30fps H.264 video and supports Wide Dynamic Range.
- $180.00

Sony IMX104

The Sony IMX104Camera Module with TI's SN65LVDS324 and TI IPCamera. It can stream 1080p@60fps H.264 video and supports 1.8V I/O interface.
- $199.00

Sony IMX136

The Sony IMX136Camera Module with TI's SN65LVDS324 and TI IPCamera. It can stream 1080p@60fps H.264 video and supports 1.8V I/O interface.
- $199.00


The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR clock by a ratio, and outputs parallel CMOS 1.8 V data on the rising clock edge. It bridges the video stream interface between HD image sensors made by leading manufacturers, to a format that common processors can accept. The supported pixel frequency is 18.5 MHz to 162 MHz — suitable for resolutions from VGA to 1080p60.

Four high-level modes are supported:
Aptina 1-Channel 4-Lane, Aptina 1-Channel 2-Lane, Panasonic 2-Channel 2-Port, and Sony LVDS Parallel. Each supports 10/12/14/16 bit sub-modes, according to Table 1. Each mode also has a configurable allowable frequency range, as specified by Table 3 register PLL_CFG.

The SN65LVDS324 is configured through its I2C-programmable registers. This volatile memory must be written after power up. Configuration options include the MSB/LSB output order, sync polarity convention, data slew rate, and two output timing modes (long-setup or clock-centered), for wider compatibility with different processors and software. The TESTMODE_VIDEO feature is designed to assist engineering development. The max allowable frame size is 8191 x 8191.

With integrated differential input termination, and a footprint of 4.5 × 7mm, the SN65LVDS324 provides a differentiated solution with optimized form, function, and cost. It operates through an ambient temperature range of –40°C to 85°C.


  • Bridges the Interface Between Video Image
    Sensors and Processors
  • Receives Aptina HiSPi™, Panasonic LVDS, or
    Sony LVDS Parallel; Outputs 1.8V CMOS with
    10/12/14/16 Bits at 18.5 MHz to 162 MHz
  • SubLVDS Inputs Support Up To:
    • Sony LVDS parallel:
      • 10-bpp: 1620 Mbps
      • 12-bpp: 1944 Mbps
    • Panasonic LVDS:
      • 1-channel 4-lane 12-bpp: 972 Mbps
      • 1-channel 4-lane 16-bpp: 1296 Mbps
      • 2-channel 2-port 12-bpp: 486 Mbps per
      • 2-channel 2-port 16-bpp: 6408 Mbps per
    • Aptina HiSPi:
      • 1-channel 4-lane 14bpp: 1134Mbps
      • 1-channel 2-lane 12bpp: 594 Mbps
  • Integrated 100-Ω Differential Input Termination
  • Test Image Generation Feature
  • Compatible with TI OMAP and DaVinci
    Including DM385, DM8127, DM36x, and DMVA
  • Low Power 1.8 V CMOS Process
  • Configurable Output Conventions
  • Packaged in 4.5 × 7mm BGA

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Parametrics Compare all products in SerDes/Channel-Link

Supply Voltage(s) (V)
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
Channel-Link I    Channel-Link I   
1.8    1.8   
Catalog    Catalog   
-40 to 85    -40 to 85   
59BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)    24VQFN: 16 mm2: 4 x 4(VQFN)   

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