High Definition Image Sensor Receiver - SN65LVDS324

SN65LVDS324 (ACTIVE)

High Definition Image Sensor Receiver



TI IPCamera Modules using the SN65LVDS324 Available Through Leopard Imaging Inc

Aptina AR0331

The Aptina AR0331Camera Module with TI's SN65LVDS324 and IPCamera DM385 with 1.8V I/O interface. Streams 1080p@60fps H.264 video.
- $150.00

Panasonic MN34041

The Panasonic MN34041Camera Module with TI's SN65LVDS324 and TI IPCamera on Leopardboard 36x. It can stream 1080p@30fps H.264 video and supports Wide Dynamic Range.
- $180.00

Sony IMX104

The Sony IMX104Camera Module with TI's SN65LVDS324 and TI IPCamera. It can stream 1080p@60fps H.264 video and supports 1.8V I/O interface.
- $199.00

Sony IMX136

The Sony IMX136Camera Module with TI's SN65LVDS324 and TI IPCamera. It can stream 1080p@60fps H.264 video and supports 1.8V I/O interface.
- $199.00

Description

The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR clock by a ratio, and outputs parallel CMOS 1.8V data on the rising clock edge. It bridges the video stream interface between HD image sensors made by leading manufacturers, to a format that common processors can accept. The supported pixel frequency is 18.5MHz to 162MHz — suitable for resolutions from VGA to 1080p60.

Four high-level modes are supported: Aptina 1-Channel 4-Lane, Aptina 1-Channel 2-Lane, Panasonic 2-Channel 2-Port, and Sony LVDS Parallel. Each supports 10/12/14/16 bit sub-modes, according to Table 1. Each mode also has a configurable allowable frequency range, as specified by Table 3 register PLL_CFG.

The SN65LVDS324 is configured through its I2C-programmable registers. This volatile memory must be written after power up. Configuration options include the MSB/LSB output order, sync polarity convention, data slew rate, and two output timing modes (long-setup or clock-centered), for wider compatibility with different processors and software. The TESTMODE_VIDEO feature is designed to assist engineering development. The max allowable frame size is 8191 × 8191.

With integrated differential input termination, and a footprint of 4.5 × 7mm, the SN65LVDS324 provides a differentiated solution with optimized form, function, and cost. It operates through an ambient temperature range of –40°C to 85°C.

Features

  • Bridges the Interface Between Video Image Sensors and Processors
  • Receives Aptina HiSPi, Panasonic LVDS, or Sony LVDS Parallel; Outputs 1.8V CMOS
    with 10/12/14/16 Bits at 18.5MHz to 162MHz
  • SubLVDS Inputs Support Up To 648Mbps
  • Integrated 100Ω Differential Input Termination
  • Test Image Generation Feature
  • Compatible with TI OMAP and DaVinci Including DM385, DM8127, DM36x, and DMVA
  • Low Power 1.8V CMOS Process
  • Configurable Output Conventions
  • Packaged in 4.5 × 7mm BGA

View more

Parametrics Compare all products in FlatLink 3G

 
Number of Parallel Outputs
Data Throughput (Mb/s)
Serial Data Receiver Channels
Supply Voltage(s) (V)
ICC (mA)
Pin/Package
Approx. Price (US$)
Operating Temperature Range (C)
Typical Active Power (mW)
SN65LVDS324
18    
324    
12    
1.8    
83    
59BGA MICROSTAR JUNIOR    
2.65 | 1ku    
-40 to 85    
150    

Featured tools and software

Companion parts

Part # Name Product Family Comments
TMS320DM365   DaVinci Digital Media Processor   ARM9 - DaVinci DM3x SOC    Sensor interface and high-performance application processor together offer total solution for IP video surveillance cameras, the interface directly converts video information from industry leading proprietary sensor formats to a standard parallel interface compatible with popular digital signal processors  
TMS320DM368   DaVinci Digital Media Processor   ARM9 + Video Core - DM3x Video SOC    Sensor interface and high-performance application processor together offer total solution for IP video surveillance cameras, the interface directly converts video information from industry leading proprietary sensor formats to a standard parallel interface compatible with popular digital signal processors  
SupplyFrame