SN7400

(ACTIVE) Quad 2-input Positive-NAND Gates

Diagram

Functional Diagram

Description

The SNx4xx00 devices contain four independent,
2-input NAND gates. The devices perform the Boolean function Y = A .B or Y = A + B in positive logic.

Features

  • Package Options Include:
    • Plastic Small-Outline (D, NS, PS)
    • Shrink Small-Outline (DB)
    • Ceramic Flat (W)
    • Ceramic Chip Carriers (FK)
    • Standard Plastic (N)
    • Ceramic (J)
  • Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package
  • Inputs Are TTL Compliant; VIH = 2 V and
    VIL = 0.8 V
  • Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
  • SN5400, SN54LS00, and SN54S00 are Characterized For Operation Over the Full Military Temperature Range of –55ºC to 125ºC

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Parametrics

Technology Family TTL    
VCC (Min) (V) 4.75    
VCC (Max) (V) 5.25    
Channels (#) 4    
Inputs per channel 2    
ICC @ nom voltage (Max) (mA) 0.022    
IOL (Max) (mA) 16    
IOH (Max) (mA) -0.4    
Input type Bipolar    
Output type Push-Pull    
Features High Speed (tpd 10-50ns)    
Rating Catalog    
Data rate (Max) (Mbps) 70    
Operating temperature range (C) 0 to 70    
Package Group PDIP|14^SOIC|14^SO|14    
Package size: mm2:W x L (PKG) See datasheet (PDIP)^14SO: 80 mm2: 7.8 x 10.2 (SO|14)^14SOIC: 52 mm2: 6 x 8.65 (SOIC|14)    

Companion Products

Technical Documents

Datasheet (1)

Application notes (6)

Selection guides (1)

Solution guides (1)

More literature (1)

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