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SN74AUP1G08

ACTIVE

1-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate

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Data sheet

SN74AUP1G08

ACTIVE
Data sheet Order now

Product details

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YFP) 6 1.4000000000000001 mm² 1 x 1.4000000000000001 DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Ultra Small 0.64 mm2 Package
    (DPW) With 0.5-mm Pitch
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 4.3 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back Drive Protection
  • Schmitt-Trigger Action Allows Slow Input
    Transition and Better Switching Noise Immunity at
    the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal
    Operation
  • tpd = 4.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64 mm2 Package
    (DPW) With 0.5-mm Pitch
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 4.3 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back Drive Protection
  • Schmitt-Trigger Action Allows Slow Input
    Transition and Better Switching Noise Immunity at
    the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal
    Operation
  • tpd = 4.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 0.8-V to 3.6-V VCC operation and performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

This single 2-input positive-AND gate is designed for 0.8-V to 3.6-V VCC operation and performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.
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Technical documentation

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Type Title Date
* Data sheet SN74AUP1G08 Low-Power Single 2-Input Positive-AND Gate datasheet (Rev. P) PDF | HTML 17 Jun 2016
Application brief Optimizing Industrial Robot CPU Boards with Logic and Voltage Translation PDF | HTML 12 Dec 2022
Application brief Optimizing WLAN and WiFi Access Point Systems With Logic and Voltage Translation PDF | HTML 03 Nov 2022
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

SN74AUP1G08 Behavioral SPICE Model

SCEM690.ZIP (7 KB) - PSpice Model
Download
Simulation model

SN74AUP1G08 IBIS Model (Rev. A)

SCEM405A.ZIP (65 KB) - IBIS Model
Download
Package Pins Download
DSBGA (YFP) 6 View options
DSBGA (YZP) 5 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options
SOT-SC70 (DCK) 5 View options
USON (DRY) 6 View options
X2SON (DPW) 5 View options
X2SON (DSF) 6 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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