4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level Shifting and 3-State Outputs - SN74AVC4T774

SN74AVC4T774 (ACTIVE)

4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level Shifting and 3-State Outputs

 

Description

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 to 3.6 V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal low-voltage bi-directional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power-up or power-down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to either a high VCC state, or a low-GND state, an undesirable larger than expected ICC current may result. Since the input voltage settlement is governed by many factors (for example, capacitance, board-layout, package inductance, surrounding conditions, and so forth), ensuring that they these inputs are kept out of erroneous switching states and tying them to either a high or a low level minimizes the leakage-current.

Features

  • Each Channel Has an Independent DIR Control Input
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
  • I/Os are 4.6-V Tolerant
  • Ioff Supports Partial Power-Down-Mode Operation
  • Typical Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds the Following Levels (Tested Per JESD 22)
    • ±8000-V Human-Body Model (A114-A)
    • 250-V Machine Model (A115-A)
    • ±1500-V Charged-Device Model (C101)

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Parametrics Compare all products in Direction Controlled Voltage Translation

 
Technology Family
Bits (#)
VCC (Min) (V)
VCC (Max) (V)
Voltage (Nom) (V)
F @ Nom Voltage (Max) (Mhz)
ICC @ Nom Voltage (Max) (mA)
Rating
Operating Temperature Range (C)
Pin/Package
SN74AVC4T774 SN74AVC4T234 SN74AVC4T245 SN74AVC4T245-Q1 SN74AVCH4T245 TXB0104 TXB0104-Q1 TXB0302 TXB0304 TXS0104E TXS0104E-Q1
AVC    AVC    AVC    AVC    AVC    TXB    TXB    TXB    TXB    TXS    TXS   
4    4    4    4    4    4    4    2    4    4    4   
1.2    0.9    1.2    1.2    1.2               
3.6    3.6    3.6    3.6    3.6               
1.2
1.5
1.8
2.5
3.3   
1.2
1.5
1.8
2.5
3.3   
1.2
1.5
1.8
2.5
3.3   
1.2
1.5
1.8
2.5
3.3   
1.2
1.5
1.8
2.5
3.3   
1.2
1.5
1.8
2.5
3.3
5   
1.2
1.5
1.8
2.5
3.3
5   
1
1.2
1.5
1.8
2.5
3.3   
1
1.2
1.5
1.8
2.5
3.3   
1.8
2.5
3.3
5   
1.8
2.5
3.3
5   
100    100    100    100    100    50    50    50    60    12    12   
0.016    0.016    0.016    0.016    0.016    0.01    0.04    0.01    0.01    0.0144    0.025   
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