The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
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To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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| Technology Family |
| VCC (Min) (V) |
| VCC (Max) (V) |
| Bits (#) |
| Voltage (Nom) (V) |
| F @ Nom Voltage (Max) (Mhz) |
| ICC @ Nom Voltage (Max) (mA) |
| tpd @ Nom Voltage (Max) (ns) |
| IOL (Max) (mA) |
| IOH (Max) (mA) |
| Schmitt Trigger |
| Rating |
| Operating Temperature Range (C) |
| Pin/Package |
| SN74LVC2G125 | SN74LVC2G125-Q1 |
|---|---|
| LVC | LVC |
| 1.65 | 1.65 |
| 5.5 | 5.5 |
| 2 | 2 |
|
1.8 2.5 3.3 5 |
1.8 2.5 3.3 5 |
| 150 | 150 |
| 0.01 | 0.01 |
|
9.1 4.8 4.3 3.7 |
9.1 4.8 4.3 3.7 |
| 32 | 32 |
| -32 | -32 |
| No | No |
| Catalog | Automotive |
| -40 to 125 | -40 to 85 |
|
8DSBGA 8SM8 8VSSOP |
8SM8 8VSSOP |
| Order Now | Order Now |
| Version | Part Number | Definition |
|---|---|---|
| Automotive | SN74LVC2G125-Q1 | Q100 devices qualified for high-reliability automotive applications targeting zero defects |
