FlatLink(TM) Receiver - SN75LVDS82


FlatLink(TM) Receiver



The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or SN75LVDS85 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low-level on SHTDN clears all internal registers to a low level and places the CMOS outputs in a high-impedance state.

The SN75LVDS82 is characterized for operation over ambient air temperatures of 0°C to 70°C.


  • 4:28 Data Channel Expansion at up to 238 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display
    Data Transmission From Controller to
    Display With Very Low EMI
  • Four Data Channels and Clock Low-Voltage
    Differential Channels In and 28 Data and
    Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply With
    250 mW (Typ)
  • 5-V Tolerant SHTDN Input
  • Falling Clock-Edge-Triggered Outputs
  • Packaged in Thin Shrink Small-Outline
    Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency
    Range . . . 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Inputs Meet or Exceed the Requirements of
    ANSI EIA/TIA-644 Standard
  • Improved Replacement for the National™ DS90C582

FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners

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Parametrics Compare all products in FlatLink/FPD-Link (LVDS for LCD)

Number of Parallel Outputs
Number of Parallel Inputs
Data Throughput (Mb/s)
Serial Data Receiver Channels
Serial Data Transmitter Channels
Type of Line Circuit
Driver (RL) (Ohms)
Receiver (Vth) (mV)
Supply Voltage(s) (V)
PLL Frequency (MHz)
Operating Temperature Range (C)
Approx. Price (US$)
Packages Size (mm x mm)
Pin Pitch (mm)
Parallel I/O Voltage (V)
28    0    0    0   
0    28    28    28   
227.5    2800    3780    2380   
4    0    0    0   
0    4    4    4   
100    100    100    100   
100    100    100    100   
3.3    3.3    3.3    3.3   
31 - 68    10 - 100    10 - 135    10 - 85   
0 to 70    -10 to 70    -10 to 70    -10 to 70   
2.57 | 1ku    2.10 | 1ku    2.60 | 1ku    2.80 | 1ku   
Catalog    Catalog    Catalog    Catalog   

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