Stereo USB Audio Interface - TAS1020B

TAS1020B (NRND)

Stereo USB Audio Interface

Not Recommended for New Designs (NRND)

Replaced By TMS320C5533 – The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.  

TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.

TI provides a sample application program for the TAS1020B. This sample application is written in the 'c' programming language, as extended for the 8052 by Keil Software, Inc. (www.keil.com). The application source is provided in the Firmware Development Kit. The sample application can be built from the FDK and runs on the TAS1020BEVM.

The Firmware Development Kit also contains source for the code in the TAS1020B internal ROM, as well as notes on how your application can use the ROM. Users of the TAS1020B will need to modify the sample application for their particular requirements (e.g., for different sample rates, DACs, ADCs, etc.). Thus, ability to write software for the 8052 is required in order to use this part.

In addition to the requirement of a Keil 8052 C compiler, standard USB product development tools such as a USB bus analyzer are recommended for development of TAS1020B based products.

Currently only 32-bit Windows development platforms are supported.

Description

The TAS1020B integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed specifically for applications that require isochronous data streaming. Applications include digital speakers, which require the streaming of digital audio data between the host PC and the speaker system via the USB connection. The TAS1020B device is fully compatible with the USB Specification Version 1.1 and the USB Audio Class 1.0 Specification.

The TAS1020B uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization, the boot loader program downloads the application program code to a 6,016-byte RAM from either the host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk endpoint transactions. DMA channels are provided to handle isochronous endpoint transactions.

The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition to the USB control endpoint, support is provided for up to seven IN endpoints and seven OUT endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint configuration blocks that reside in on-chip RAM. All USB data transfer types are supported.

The TAS1020B device also includes a codec port interface (C-Port) that can be configured to support several industry standard serial interface protocols. These protocols include the audio codec (AC) ’97 Revision 1.X, the AC ’97 Revision 2.X and several inter-IC sound (I2S) modes.

A direct memory access (DMA) controller with two channels is provided for streaming the USB isochronous data packets to/from the codec port interface. Each DMA channel can support one USB isochronous endpoint.

An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization modes, which include asynchronous, synchronous and adaptive.

Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit general-purpose input/output (GPIO) ports.

The TAS1020B device is implemented in a 3.3-V 0.25 µm CMOS technology.

The 8K ROM is mask-programmed as part of the TAS1020B manufacturing process. The ROM program provides the boot behavior as discussed in . It also provides support functions for the user’s application. Source for the ROM image is provided in the TAS1020B Firmware Development Kit (http://focus.ti.com/docs/toolsw/folders/print/tas1020fdk.html).

This section describes the TAS1020B MCU memory configurations and operation. In general, the MCU memory operation is the same as the industry standard 8052 MCU.

Features

  • Universal Serial Bus (USB)
    • USB specification version 1.1 compatible
    • USB audio class specification 1.0 compatible
    • Integrated USB transceiver
    • Supports 12 Mb/s data rate (full speed)
    • Supports suspend/resume and remote wake-up
    • Supports control, interrupt, bulk, and isochronous data transfer type
    • Supports up to a total of seven IN endpoints and seven OUT endpoints
      in addition to the control endpoint
    • Data transfer type, data buffer size, single or double buffering is
      programmable for each endpoint
    • On-chip adaptive clock generator (ACG) supports asynchronous, synchronous
      and adaptive synchronization modes for isochronous endpoints
    • To support synchronization for streaming USB audio data, the ACG can be used
      to generate the master clock for the codec
  • Micro-Controller Unit (MCU)
    • Standard 8052 8-bit core
    • 8K bytes of program memory ROM that contains a boot loader program and a
      library of commonly used USB functions
    • 6016 bytes of program memory RAM which is loaded by the boot loader program
    • 256 bytes of internal data memory RAM
    • Two GPIO ports
    • MCU handles all USB control, interrupt, and bulk endpoint transfers
  • DMA Controller
    • Two DMA channels to support streaming USB audio data to/from
      the codec port interface
    • Each channel can support a single USB isochronous endpoint
    • In the I2S mode the device can support DAC/ADCs at
      different sampling frequencies
    • A circular programmable FIFO used for isochronous audio data streaming
  • Codec Port Interface
    • Configurable to support AC '97 1.x, AC '97 2.x, AIC,
      or I2S serial interface formats
    • I2S modes can support a combination of one stereo DAC
      and/or two stereo ADCs
    • Can be configured as a general-purpose serial interface
    • Can support bulk data transfer using DMA for higher throughput
  • I2C Interface
    • Master only interface
    • Does not support a multimaster bus environment
    • Programmable to 100 kb/s or 400 kb/s data transfer speeds
    • Supports wait states to accommodate slow slaves
  • General Characteristics
    • High performance 48-pin TQFP Package
    • On-chip phase-locked loop (PLL) with internal oscillator is used to
      generate internal clocks from a 6 MHz crystal input
    • Reset output available which is asserted for both system and USB reset
    • External MCU mode supports application firmware development
    • 8K ROM with boot loader program and commonly used USB functions library
    • 3.3 V core and I/O buffers

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