The TCA9517-Q1 is a bidirectional buffer with level shifting capabilities for I2C and SMBus systems. It supplies bidirectional voltage-level translation (up-translation/ down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.25 V) in mixed-mode applications. This device enables I2C and SMBus systems to be extended without loss of performance, even during level shifting.
The TCA9517-Q1 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of up to 400-pF bus capacitance to be connected in an I2C application.
The TCA9517-Q1 has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are overvoltage tolerant to 5.25 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).
The buffer design on the B-side prevents its use in series with devices that use static voltage offset. The devices do not recognize buffered low signals as a valid low, and do not propagate it as a buffered low again.
The B-side drivers operate from 2.7 V to 5.25 V. The output low level for this internal buffer is approximately 0.5 V. The input voltage must be more than 70 mV below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.
The A-side drivers operate from 0.9 V to 5.25 V, and drive more current. They do not require the buffered low feature (or the static offset voltage). A low signal on the B-side translates to a nearly 0 V low on the A-side. This accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A-side drives a hard low. The input level is set at 0.3 × VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V.
The A-side of two or more TCA9517-Q1 devices can be connected together. This allows many topographies (See Figure 8 and Figure 9 ) with the A-side as the common bus. The A-side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple TCA9517-Q1 devices can be connected in series, A-side to B-side, with no buildup in offset voltage, and with only time-of-flight delays to consider. The TCA9517-Q1 cannot be connected B-side to B-side, because of the buffered low voltage from the B-side. The B-side cannot be connected to a device with rise time accelerators.
VCCA is only used to provide the 0.3 × VCCA reference to the A-side input comparators and for the power-good-detect circuit. The TCA9517-Q1 logic and all I/Os are powered by the VCCB pin.
As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The TCA9517-Q1 has standard open-drain configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Higher termination currents can be used in some cases.
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|VCCA (Min) (V)|
|VCCA (Max) (V)|
|VCCB (Min) (V)|
|VCCB (Max) (V)|
|Frequency (Max) (kHz)|
|Operating Temperature Range (C)|
|Approx. Price (US$)|
|No rule||VCCA <= VCCB||No rule||No rule|
|-40 to 125||
-40 to 105
-40 to 85
|-40 to 85||-40 to 85|
|VSSOP | 8||VSSOP | 8||
SOIC | 8
VSSOP | 8
|VSSOP | 8|
|0.51 | 1ku||0.24 | 1ku||0.34 | 1ku||0.34 | 1ku|
|Order Now||Order Now||Order Now||Order Now|