The TCI6630K2L Communications Infrastructure KeyStone SoC is a member of the C66x family based on TIs new KeyStone II Multicore SoC Architecture and is a low-power baseband solution with integrated digital front end (DFE) that meets the more stringent power, size, and cost requirements of small cell wireless base stations. In enterprise and pico base stations, the devices ARM and DSP cores deliver exceptional processing power on platforms for developing all wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.
TIs KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The addition of the ARM CorePac in the TCI6630 enables the ability for layer 2 and layer 3 processing on-chip. Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor.
TIs new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for algorithms like MIMO and beamforming.
The TCI6630K2L contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 basestation processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP), which handles the entire downlink bit-processing chain and much of the receive bit processing. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.
TIs scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse across all basestation platforms from Femto to Macro.
The TCI6630K2L device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.