TCI6638K2K (PREVIEW)

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Description

TheTCI6638K2K Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture designed for high performance wireless infrastructure applications. The TCI66368K2K provides an ultra-high performance small cell basestation platform supporting wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, LTE-A, and WiMAX.

TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (Quad ARM Cortex-A15 CorePAc, C66x DSP CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly.

Features

  • Eight TMS320C66x DSP Core Subsystems Per Core @ 1.2 GHz
    • 307 GMAC/153 GFLOP @ 1.2 GHz
    • 32KB L1P, 32KB L1D, 1024KB L2 Per Core
  • ARM Cortex A15 Quad Core Cluster @ 1.2 GHz Per Core with 4MB L2 Cache Coherent Memory
  • 6MB Multicore Shared L3 Memory Across DSP and ARM
  • Non-blocking Chip Infrastructure with Multicore Navigator and 2.2 Tb TeraNet Switch Fabric
  • Network Coprocessor - Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • Two HyperLink - 50 Gbaud Operation per HyperLink, Full Duplex
  • Ethernet MAC Subsystem - Four SGMII Ports w/ 10/100/1000 Mbps Switches
  • Three-port 10Gb Ethernet switch
  • Two 64-Bit DDR3 Interfaces (DDR3-1600) - 8 GByte Addressable Memory Space
  • Six Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps
  • Hardware Coprocessors
    • Bit Rate Coprocessor
    • Four Enhanced Coprocessors for Turbo Decoding
    • Eight Viterbi Decoders
    • Six Fast Fourier Transform Coprocessors
    • Two WCDMA Receive Accelerators and One WCDMA Transmit Accelerator
  • Sixteen Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding
  • I2C, SPI, USB 3.0, 16-bit ASYNC EMIF, and USIM Interfaces.
  • Twenty 64-Bit Timers, Five On-Chip PLLs, and 32 GPIO Pins

View more
Click Here