TCI6638K2K (ACTIVE)

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

 

Description

The TCI6638K2K Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI’s new KeyStone II Multicore SoC Architecture designed specifically for high performance wireless infrastructure applications. The TCI6638K2K provides a very high performance macro base station platform for developing all wireless standards, including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed I/O, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the TCI6638K2K enables the ability for layer 2 and layer 3 processing on-chip. Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math-oriented (VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for algorithms like MIMO and beamforming.

The TCI6638K2K contains many wireless base station coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 base station processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP), which handles the entire downlink bit-processing chain and much of the receive bit processing. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse across all base station platforms from Femto to Macro.

The TCI6638K2K device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

Features

  • Eight TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-
      Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors
      at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low-
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight
      DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM
      SRAM and DDR3_EMIF
  • Hardware Coprocessors
    • Four Turbo Decoders
      • Supports WCDMA/HSPA/HSPA+/TD-
        SCDMA, LTE, LTE-A, and WiMAX
      • Supports up to 530 Mbps for LTE at Block
        Size 6144, 8 Iterations and up to 400 Mbps
        for WCDMA at Block Size 5114, 8 Iterations
      • Low DSP Overhead – Hardware Interleaver
        Table Generation and CRC Check
    • Eight Viterbi Decoders
      • Supports up to 96 Mbps (Length 9, Rate 1/2,
        Block Size 6000)
    • Four WCDMA Receive Acceleration
      Coprocessors
      • Supports up to 8192 Correlators
    • WCDMA Transmit Acceleration Coprocessor
      • Supports up to 2304 Spreaders
    • Six Fast Fourier Transform (FFT) Coprocessors
      • Support up to 600 Mscps/FFTC at FFT Size
        1024
    • Bit Rate Coprocessor
      • WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A,
        and WiMAX Uplink and Downlink Bit
        Processing
      • Includes Encoding, Rate
        Matching/Dematching, Segmentation,
        Multiplexing, and More
      • Supports up to DL 1525 Mbps and UL 1030
        (on-chip) or 680 (DDR3) Mbsp for LTE and
        DL 784 Mbps and UL 395 Mbsp for
        WCDMA/TD-SCDMA
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With
      Queue Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit
        Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Sixteen Rake/Search Accelerators (RSA) for
    • Chip Rate Processing for WCDMA Rel'99,
      HSDPA, and HSDPA+
    • Reed-Muller Decoding
  • Peripherals
    • Six-Lane SerDes-Based Antenna Interface
      (AIF2)
      • Operating at up to 6.144 Gbps
      • Compliant With OBSAI RP3 and CPRI
        Standards for 3G and 4G (WCDMA, LTE
        TDD, LTE FDD, TD-SCDMA, and WiMAX)
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud, Direct I/O,
        Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone
        Architecture Devices Providing Resource
        Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
    • Two 72-Bit DDR3 Interfaces With Speeds up to
      1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • Twenty 64-Bit Timers
    • Five On-Chip Phase-Locked Loops (PLLs)
  • Commercial Case Temperature:
    • 0°C to 100°C
  • Extended Case Temperature:
    • –40°C to 100°C

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Related end equipment

  • Macro base station

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