SoC Processor for Advanced Driver Assist Systems (ADAS)

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Learn more about the TDAx SoC for Advanced Driver Assistance Systems (ADAS).

Special Note

This product family is available for high volume Automotive manufacturers. Please contact your TI sales representative for more details.


TDA2x Advanced Driver Assistance Systems (ADAS) applications processors are a highly integrated, programmable platform that leverages TI’s OMAP™ technology to meet the intense processing needs of the modern infotainment-enabled automobile.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core ARM Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more embedded vision engines). The ARM allows developers to keep control functions separate from vision algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

The TMS320C66x (C66x) DSP core is the next-generation fixed and floating-point DSP in the C6000™ DSP family. The new C66x DSP enhances the C674x with 4x the multiply operations per cycle, expanded SIMD support for floating-point operations, improved floating-point arithmetic, and enhanced vector processing capabilities for fixed and floating point.

TDA2x ADAS Applications Processors also includes the programmable Vision AccelerationPac with embedded vision engines (EVEs) to off-load many video analytics processing tasks from the DSP core, making more DSP engines available for mid- and high-level analytics processing.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the complete data manual or technical reference manual for the device. Available peripheral sets include an image video accelrator (IVA-HD), a single-port gigabit ethernet MAC (GMAC), dual controller area network (DCAN) interfaces, a PCI Express 2.0 port with integrated physical layer, 16-channel McASP, 10 UARTs with support for IrDA and CIR support, four McSPI, five I2C master/slave interfaces; a multichannel video input port (VIP) supporting up to 10 multiplexed connections, up to 256 GPIO pins; sixteen 32-bit general-purpose timers; a system watchdog timer; DDR2 and DDR3 memory controllers. For a complete list of available peripherals, see the device data manual.

Additionally, Texas Instruments provides a complete set of development tools for the ARM, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, a debugging interface for visibility into source code execution, and the new WEBENCH® Automotive Design Tool from

The TDA2x ADAS processor is qualified according to AEC-Q100 standard.


  • Architecture Designed for ADAS Applications
    • Best-in-Class CPU Performance
    • State-of-the-Art Integrated Power Management
    • Video, Image, and Graphics Processing Support
      • Streaming Full-HD Video (1920x1080p, 60 fps)
      • Multiple Video Input and Video Output
      • 2D and 3D Graphics
  • ARM® Dual Cortex™-A15 Microprocessor Subsystem
  • C66x™ Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x™ and C64x+™
    • Up to Thirty-two 16 x 16-bit Fixed-point Multiplies per Cycle
  • Up to 2.5 MiB of On-Chip L3 RAM
  • 768-Bit Interface to Internal RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3 Memory Interface (EMIF) Modules
    • Supports up to DDR2-667 and DDR3-667
    • Up to 2-GiB Supported per EMIF
  • ARM Cortex™-M4 Image Processor (IPU)
    • Two Dual-core, 200 MHz per Core
  • Vision AccelerationPac
    • Up to Four Embedded Vision Engines (EVEs)
  • IVA-HD Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and Up to Three Pipelines
    • HDMI Encoder: HDMI 1.4a, HDCP 1.4, and DVI 1.0 Compliant
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante™ GC320 Core
  • Video Processing Engine (VPE)
  • Available Dual-Core PowerVR® SGX544™ 3D GPU
  • Up to 3 Video Input Port (VIP) Module Instances
    • Support for Up to 10 Multiplexed Input Ports
  • Available Programmable Real-time Unit (PRU) Subsystem
    • Interrupt Controller Supporting 64 Input Events
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 3-Port Gigabit Ethernet (GMAC)
    • Up to Two External Ports, One Internal
  • Dual Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • PCI Express 2.0 Port with Integrated PHY
    • Single Port With 1 Lane at 5.0 Gbps
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (MCSPIs)
  • Five Inter-Integrated Circuit (I2C) Ports
  • Multichannel Audio Serial Port (MCASP)
  • Up to 256 General-Purpose I/O (GPIO) Pins
  • Power, Reset, and Clock Management
    • SmartReflex™ Class-1 Technology
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Clock Management (CM) Allows Reduction of Dynamic Consumption
  • On-Chip Debug with CTools Technology
  • Automotive AEC-Q100 Qualified
  • 28-nm CMOS Technology
  • The ADAS Vision28 Will Be Offered with Two Package Options:
    • 23-mm Package (ABC Suffix)
      • Ball Grid Array (BGA)
      • 0.8-mm Ball Pitch with Via Channel Array (VCA)
      • Partial Grid
      • 760 Device Pins
    • 17-mm Package (AAS Suffix)
      • BGA
      • 0.65-mm Ball Pitch with Microvia
      • Full Grid
      • 625 Device Pins

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