The TLK10002 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high speed applications. It supports all the CPRI and OBSAI rates from 1.2288Gbps to 9.8304Gbps.
The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5Gbps to 5Gbps and the high speed side data rate can range from 1Gbps to 10Gbps. Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.
The TLK10002 performs data serialization/deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side.
The TLK10002 provides two low speed side and two high speed side loopback modes for self-test and system diagnostic purposes.
The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high speed side supports High, Low, Mixed, and CRPAT long/short pattern generation and verification.
The TLK10002 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.
Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.
The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.
The low speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.
|Approx. Price (US$)|
|Operating Temperature Range (C)|
|25.00 | 1ku|
|-40 to 85|
|Sample & Buy|
|Part #||Name||Product Family||Comments|
|SN65LVCP404||4 x 4 LVDS Crosspoint Switch||LVDS/M-LVDS/ECL/CML - Crosspoint-Switch||4 X 4 LVDS Crosspoint Switch|
|SN65LVCP408||8x8 4.25Gbps Crosspoint Switch||LVDS/M-LVDS/ECL/CML - Crosspoint-Switch||8 X 8 4.25Gbps Crosspoint Switch|