TLK10002 (ACTIVE)

Dual-Channel 10Gbps Multi-Rate Transceiver

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Description

The TLK10002 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high speed applications. It supports all the CPRI and OBSAI rates from 1.2288Gbps to 9.8304Gbps.

The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5Gbps to 5Gbps and the high speed side data rate can range from 1Gbps to 10Gbps. Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.

The TLK10002 performs data serialization/deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side.

The TLK10002 provides two low speed side and two high speed side loopback modes for self-test and system diagnostic purposes.

The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high speed side supports High, Low, Mixed, and CRPAT long/short pattern generation and verification.

The TLK10002 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.

Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.

Features

  • Dual Channel 10Gbps Multi-Rate Transceiver
  • Supports all CPRI and OBSAI Data Rates From 1Gbps to 10Gbps
  • Integrated Latency Measurement Function, Accuracy up to 814 ps
  • Supports SERDES Operation with up to 10Gbps Data Rate on the High Speed Side and up to 5Gbps on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Shared or Independent Reference Clock per Channel
  • Loopback Capability on Both High Speed and Low Speed Sides, OBSAI Compliant
  • Supports Data Retime Operation
  • Supports PRBS 27-1, 223-1 and 231-1 and High-Frequency/Low-Frequency/Mixed-Frequency/CRPAT Long/Short Pattern Generation and Verification
  • Two Power Supplies: 1.0V Core, and 1.5 or 1.8V I/O
  • Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed and Low Speed Sides
  • Programmable Transmit Output Swing on Both High Speed and Low Speed Sides.
  • Minimum Receiver Differential Input Threshold of 100mVpp
  • Loss of Signal (LOS) Detection
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP/SFP+ Optical Modules
  • Hot Plug Protection
  • JTAG; IEEE 1149.1 Test Interface
  • MDIO; IEEE 802.3 Clause-22 Support
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Power Consumption: 1.6W Typical
  • Device Package: 13mm x 13mm, 144-pin PBGA, 1-mm Ball-Pitch

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Parametrics Compare all products in Telecom & Wireless Ser/Des

 
Pin/Package
Approx. Price (US$)
Operating Temperature Range (C)
TLK10002
144FCBGA    
25.00 | 1ku    
-40 to 85    

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