TMS320C40 Digital Signal Processors |

TMS320C40 (NRND)

Digital Signal Processors

Digital Signal Processors - TMS320C40

Not Recommended for New Designs (NRND)

Replaced By TMS320C6727B – The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.

TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.


The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth generation of DSPs from Texas Instruments and is designed primarily for parallel processing.


  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • '320C40-60:
      33-ns Instruction Cycle Time,
      330 MOPS, 60 MFLOPS,
      30 MIPS, 384M Bytes/s
    • '320C40-50:
      40-ns Instruction Cycle Time
    • '320C40-40:
      50-ns Instruction Cycle Time
  • Six Communications Ports
  • Six-Channel Direct Memory Access (DMA) Coprocessor
  • Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
  • Single Cycle, 1/x, 1/
  • Source-Code Compatible With TMS320C3x
  • Single-Cycle 40-Bit Floating-Point,
    32-Bit Integer Multipliers
  • Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
  • IEEE 1149.1 (JTAG) Boundary Scan Compatible
  • Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
    • High Port-Data Rate of 120M Bytes/s ('C40-60) (Each Bus)
    • 16G-Byte Continuous Program/Data/Peripheral Address Space
    • Memory-Access Request for Fast, Intelligent Bus Arbitration
    • Separate Address-Bus, Data-Bus, and Control-Enable Pins
    • Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
  • 325-Pin Ceramic Grid Array (GF Suffix)
  • Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPICTM) Technology by Texas Instruments (TITM)
  • Software-Communication-Port Reset
  • NMI\ With Bus-Grant Feature
  • Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
  • On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
    • 512-Byte Instruction Cache
    • 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
    • ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
  • IDLE2 Clock-Stop Power-Down Mode
  • 5-V Operation

    IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture
    EPIC and TI are trademarks of Texas Instruments Incorporated.

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