Multicore Fixed and Floating-Point System-on-Chip - TMS320C6670

TMS320C6670 (ACTIVE)

Multicore Fixed and Floating-Point System-on-Chip

 

Description

The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

Features

  • Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.2GHz
    • 153.6 GMAC/76.8 GFLOP @ 1.2GHz
    • 32KB L1P, 32KB L1D, 1024KB L2 Per Core
    • 2MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessors- Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
  • Six Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps
  • Hardware Coprocessors
    • -Enhanced Coprocessor for Turbo Encoding
      -Three Enhanced Coprocessors for Turbo Decoding
      -Four Viterbi Decoders
      -Three Fast Fourier Transform Coprocessors
      -Bit Rate CoProcessor
      -Two Receiver Accelerators for WCDMA
      -Transmitt Accelerator for WCDMA
  • Four Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding
  • I2C Interface, 16 GPIO Pins, SPI Interface
  • Eight 64-Bit Timers, Three On-Chip PLLs

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Parametrics Compare all products in C66x DSP

 
Applications
DSP
DSP MHz (Max.)
GFLOPS
Total On-Chip Memory (KB)
On-Chip L2 Cache
EMAC
PCI/PCIe
Serial I/O
Operating Temperature Range (C)
DRAM
Other On-Chip Memory
Hardware Accelerators
Package Size: mm2:W x L (PKG)
TMS320C6670 TMS320C6671 TMS320C6672 TMS320C6674 TMS320C6678
Communications and Telecom    Communications and Telecom    Communications and Telecom    Communications and Telecom    Communications and Telecom   
4 C66x    1 C66x    2 C66x    4 C66x    8 C66x   
1000
1200   
1000
1250   
1000
1250
1500   
1000    1000
1250   
64
76.8   
16
20   
32
40
48   
64
80   
128
160   
6528    4800    5376    6528    8832   
4096 KB    512 KB    1024 KB    2048 KB    4096 KB   
10/100/1000    2-Port 1Gb Switch    2-Port 1Gb Switch    2-Port 1Gb Switch    2-Port 1Gb Switch   
2 PCIe Gen2    2 PCIe Gen2    2 PCIe Gen2    2 PCIe Gen2    2 PCIe Gen2   
AIF2
I2C
RapidIO
SPI
UART   
I2C
RapidIO
SPI
TSIP
UART   
I2C
RapidIO
SPI
TSIP
UART   
I2C
RapidIO
SPI
TSIP
UART   
I2C
RapidIO
SPI
TSIP
UART   
-40 to 100
0 to 85   
-40 to 100
0 to 85   
-40 to 100
0 to 85   
-40 to 100
0 to 85   
-40 to 100
0 to 85   
DDR3    DDR3    DDR3    DDR3    DDR3   
2048 KB    4096 KB    4096 KB    4096 KB    4096 KB   
VCP2
TCP3d
TCP3e
FFT Coprocessor   
0    0    0    0   
See datasheet (FCBGA)    See datasheet (FCBGA)    See datasheet (FCBGA)    See datasheet (FCBGA)    See datasheet (FCBGA)