TMS320TCI6614 (ACTIVE)

Communications Infrastructure KeyStone System-on-Chip

Description

The TMS320TCI6614 Communications Infrastructure SoC is based on TI's KeyStone multicore architecture. It enables small cell base stations with radio accelerators, network and security coprocessors, fixed- and floating-point capable DSP cores, and an ARM RISC processor. Based on a 40-nm process technology, the multimode TCI6614 delivers up to 4.8 GHz of DSP processing power to enable baseband solutions for GSM, CDMA, WCDMA, TD-SCDMA, WiMAX, FDD-LTE, and TDD-LTE applications in metro, pico, and enterprise base stations.

Features

  • Four TMS320C66x DSP CorePacs @ 1.2GHz
    • 153.6 GMAC/76.8 GFLOP @ 1.2GHz
    • 32KB L1P, 32KB L1D, 1024KB L2 Per Core
    • 2MB Shared L2
  • ARM Cortex A8 Microprocessor
  • Field-Proven Wireless Software Libraries
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessor with Packet Accelerator and Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50 Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps Operation
  • 64-Bit DDR3 Interface (DDR3-1333) - 8 GByte Addressable Memory Space
  • Six-Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps
  • Universal Subscriber Identity Module (USIM) for User Authentication
  • Hardware Coprocessors
    • Bit Rate Coprocessor
    • Two Enhanced Coprocessors for Turbo Decoding
    • Four Viterbi Decoders
    • Two Fast Fourier Transform Coprocessors
    • Two WCDMA Receive Accelerators and One WCDMA Transmit Accelerator
    • Four Rake Search Accelerators for Chip-Rate Processing and Reed-Muller Decoding

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