TMS320TCI6618 (ACTIVE)

Communications Infrastructure KeyStone System-on-Chip

Description

The TMS320TCI6618 Communications Infrastructure SoC is a member of the KeyStone family of devices. It is based on TI's KeyStone multicore SoC architecture which uses the C66x DSP core. Designed specifically for multi standard 2G, 3G and 4G operation, the TCI6618 delivers double the LTE performance of previous solutions, while reducing SoC power consumption for macro and compact base stations to 0.075 mW/GMAC of power. Based on a 40-nm process technology, the TCI6618 macro basestation platform delivers 4.8 GHz of DSP processing power to support wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.

Features

  • Four TMS320C66x DSP CorePacs@ 1.2GHz
    • 153.6 GMAC/76.8 GFLOP @ 1.2GHz
    • 32KB L1P, 32KB L1D, 1024KB L2 Per Core
    • 2MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessor with Packet Accelerator and Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1333) - 8 GByte Addressable Memory Space
  • Six Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps
  • Hardware Coprocessors
    • Bit Rate Coprocessor
    • Enhanced Coprocessor for Turbo Encoding
    • Three Enhanced Coprocessors for Turbo Decoding
    • Four Viterbi Decoders
    • Three Fast Fourier Transform Coprocessors
    • Two WCDMA Receive Accelerators and One WCDMA Transmit Accelerator
    • Four Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding
  • I2C Interface, 16 GPIO Pins, SPI Interface
  • Eight 64-Bit Timers, Three On-Chip PLLs

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