The TMS320VC5410A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5410A also includes the control mechanisms to manage interrupts, repeated operations, and function calls.
(1) The on-chip oscillator is not available on all 5410A devices. For applicable devices, see the TMS320VC5410A Digital Signal Processor Silicon Errata (literature number SPRZ187).
(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307).
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