The TMS320VC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the '549) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The '549 also utilizes a highly specialized instruction set, which is the basis of its operational flexibility and speed.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the '549 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the TMS320VC549 DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional overview and should be used in conjunction with this data sheet.
For the 144-pin TQFP, the letter B in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes buffered serial port (BSP), where n = 0 or 1 port. The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes time-division multiplexed (TDM) serial port.
The pin assignments table to follow lists each signal quadrant and BGA ball pin number for the 144-pin BGA package.
The '549 signal descriptions table lists each terminal name, function, and operating mode(s).
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: The data provided in this data sheet for the 8.3-ns, 120 MIPS device is considered to be Product Preview data as the devices have not completed reliability performance qualification testing according to TI Quality Systems Specifications.
|DSP Instruction Type|
|DSP MHz (Max.)|
|DSP Peak MMACS|
|General Purpose Memory|
|IO Supply (V)|
|Operating Temperature Range (C)|
| Communications and Telecom |
| 100 |
| 100 |
|1 8-bit HPI|
|-40 to 100|
| 144BGA MICROSTAR |