TMS320VC5503

ACTIVE

Product details

DSP type 1 C55x DSP (max) (MHz) 108, 144, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 1 C55x DSP (max) (MHz) 108, 144, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PGE) 144 484 mm² 22 x 22 NFBGA (ZAY) 179 144 mm² 12 x 12
  • High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 32K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
    • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os

C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

  • High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 32K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
    • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os

C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby mode for more than 60% to 70% of the time. For applications that require more than 64K bytes of on-chip memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5503 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5503 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters,

The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby mode for more than 60% to 70% of the time. For applications that require more than 64K bytes of on-chip memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5503 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5503 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters,

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Technical documentation

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Type Title Date
* Data sheet TMS320VC5503 Fixed-Point Digital Signal Processor datasheet (Rev. J) 22 Jan 2008
* Errata TMS320VC5503 Digital Signal Processor Silicon Errata (Rev. C) 14 Apr 2008
* Errata TMS320VC5503/VC5506/VC5507/VC5509A Microstar BGA Discontinued and Redesigned 10 May 2022
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 15 Dec 2011
User guide TMS320VC5503/5507/5509 DSP Host Port Interface (HPI) Reference Guide (Rev. C) 11 Jun 2009
Application note Board and System Design Considerations for the TMS320VC5503/06/07/09A DSPs 19 Nov 2008
Application note TMS320VC5503/VC5506/VC5507/C5509A Power Consumption Summary (Rev. C) 05 Sep 2008
Application note Using the TMS320VC5503/C5506/C5507/C5509/C5509A Bootloader (Rev. F) 05 Sep 2008
User guide TMS320VC5503/5507/5509/5510 Direct Memory Access(DMA) Controller Reference Guide (Rev. E) 09 Jan 2007
User guide TMS320VC5503/5507/5509/5510 DSP Timers Reference Guide (Rev. C) 11 Apr 2006
User guide TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D) 17 Oct 2005
User guide TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) 14 Apr 2005
Application note Recommended Power Solutions For TMS320C5509A/07/03 28 Mar 2005
User guide TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 24 Feb 2005
Application note TMS320VC5503 Hardware Designer's Resource Guide 25 Jun 2004
User guide TMS320VC5503/5507/5509 DSP Real-Time Clock (RTC) Reference Guide (Rev. B) 25 Jun 2004
User guide TMS320VC5503/5507/5509 DSP External Memory Interface (EMIF) Reference Guide (Rev. A) 04 Jun 2004
User guide TMS320C55x DSP CPU Reference Guide (Rev. F) 25 Feb 2004
User guide TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G) 11 Oct 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Driver or library

SPRC100 — TMS320C55x DSP Library (DSPLIB)

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE, configuration, compiler or debugger

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Launch Download options
Software codec

C55XCODECSAUD Audio Codecs for C55x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
OMAP5912 Applications processor
Digital signal processors (DSPs)
SM320VC5507-EP Enhanced product low power C5507 fixed point DSP TMS320VC5501 Low power C55x fixed point DSP- up to 300MHz TMS320VC5502 Fixed-Point Digital Signal Processor TMS320VC5503 Low power C55x fixed point DSP- up to 200MHz TMS320VC5505 Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface, FFT HWA, SAR ADC TMS320VC5506 Low power C55x fixed point DSP - 108MHz TMS320VC5507 Fixed-Point Digital Signal Processor TMS320VC5509A Fixed-Point Digital Signal Processor TMS320VC5510A Fixed-Point Digital Signal Processors
Download options
Software codec

C55XCODECSPCH Speech Codecs for C55x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
OMAP5912 Applications processor
Digital signal processors (DSPs)
SM320VC5507-EP Enhanced product low power C5507 fixed point DSP TMS320VC5501 Low power C55x fixed point DSP- up to 300MHz TMS320VC5502 Fixed-Point Digital Signal Processor TMS320VC5503 Low power C55x fixed point DSP- up to 200MHz TMS320VC5505 Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface, FFT HWA, SAR ADC TMS320VC5506 Low power C55x fixed point DSP - 108MHz TMS320VC5507 Fixed-Point Digital Signal Processor TMS320VC5509A Fixed-Point Digital Signal Processor TMS320VC5510A Fixed-Point Digital Signal Processors
Download options
Simulation model

VC5503 GHH BSDL Model

SPRM208.ZIP (6 KB) - BSDL Model
Simulation model

VC5503 GHH IBIS Model

SPRM474.ZIP (88 KB) - IBIS Model
Simulation model

VC5503 PGE BSDL Model

SPRM209.ZIP (6 KB) - BSDL Model
Simulation model

VC5503 PGE IBIS Model

SPRM475.ZIP (87 KB) - IBIS Model
Package Pins CAD symbols, footprints & 3D models
LQFP (PGE) 144 Ultra Librarian
NFBGA (ZAY) 179 Ultra Librarian

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

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