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TPS54325

ACTIVE

4.5V to 18V Input, 3A Synchronous Step-Down Converter

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Data sheet

TPS54325

ACTIVE
Data sheet Order now

Product details

Iout (max) (A) 3 Vin (min) (V) 4.5 Vin (max) (V) 18 Type Converter Switching frequency (min) (kHz) 700 Switching frequency (max) (kHz) 700
Iout (max) (A) 3 Vin (min) (V) 4.5 Vin (max) (V) 18 Type Converter Switching frequency (min) (kHz) 700 Switching frequency (max) (kHz) 700
HTSSOP (PWP) 14 32 mm² 5 x 6.4
  • D-CAP2™ Mode Enables Fast Transient Response
  • Low Output Ripple and Allows Ceramic Output Capacitor
  • Wide VCC Input Voltage Range: 4.5 V to 18 V
  • Wide VIN Input Voltage Range: 2.0 V to 18 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Highly Efficient Integrated FET’s Optimized for
    Lower Duty Cycle Applications – 120 mΩ (High Side)
    and 70 mΩ (Low Side)
  • High Efficiency, less than 10 µA at shutdown
  • High Initial Bandgap Reference Accuracy
  • Adjustable Soft Start
  • Pre-Biased Soft Start
  • 700-kHz Switching Frequency (fSW)
  • Cycle By Cycle Over Current Limit
  • Power Good Output
  • D-CAP2™ Mode Enables Fast Transient Response
  • Low Output Ripple and Allows Ceramic Output Capacitor
  • Wide VCC Input Voltage Range: 4.5 V to 18 V
  • Wide VIN Input Voltage Range: 2.0 V to 18 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Highly Efficient Integrated FET’s Optimized for
    Lower Duty Cycle Applications – 120 mΩ (High Side)
    and 70 mΩ (Low Side)
  • High Efficiency, less than 10 µA at shutdown
  • High Initial Bandgap Reference Accuracy
  • Adjustable Soft Start
  • Pre-Biased Soft Start
  • 700-kHz Switching Frequency (fSW)
  • Cycle By Cycle Over Current Limit
  • Power Good Output

The TPS54325 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325 device enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.

The main control loop for the TPS54325 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C.

The TPS54325 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325 device enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.

The main control loop for the TPS54325 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C.
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Technical documentation

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Type Title Date
* Data sheet TPS54325 4.5-V to 18-V, 3-A Output Synchronous Step Down Switcher with Integrated FET datasheet (Rev. F) PDF | HTML 23 Nov 2014
Analog Design Journal Control-Mode Quick Reference Guide (Rev. B) PDF | HTML 29 Aug 2023
User guide TPS54325 Step-Down Converter Evaluation Module User's Guide (Rev. A) PDF | HTML 11 Oct 2021
Application note D-CAP2 Frequency Response Model, based on frequency domain analysis of Fixed On- 02 Jan 2013
Application note Understanding Thermal Dissipation and Design of a Heatsink 04 May 2011
Analog Design Journal Efficiency of synchronous versus nonsynchronous buck converters 04 Oct 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS54325EVM — 5V to 17V Input, 3A Converter Evaluation Module

The TPS54325EVM (evaluation module) is a fully assembled and tested circuit for evaluating the TPS54428 synchronous step-down converter. The EVM operates from a 4.5-V to 18-V input and provides a 1.05-V output up to 3-A load. The main control loop of TPS54325 uses D-CAP2™ mode control, which (...)

User guide: PDF | HTML
Not available on TI.com
Simulation model

TPS54325 TINA-TI Reference Design

SLVM201.TSC (168 KB) - TINA-TI Reference Design
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Simulation model

TPS54325 TINA-TI Transient Spice Model

SLVM200.ZIP (40 KB) - TINA-TI Spice Model
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Simulation model

TPS54325 Unencrypted PSpice Transient Model Package (Rev. A)

SLIM285A.ZIP (41 KB) - PSpice Model
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Reference designs

TIDA-010011 — High efficiency power supply architecture reference design for protection relay processor module

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
Schematic: PDF
Reference designs

PMP5411 — Universal AC 40W Set Top Box Power Supply (1.2V @ 3A)

This reference evaluation module is an example of complete power-trees inside a set-top-box.
It performs an AC-DC conversion, then, DC-DC conversions for 1.2V/1.8V/2.5V/3.3V/5V rails.
Test report: PDF
Schematic: PDF
Reference designs

PMP8251 — Power Solution for Xilinx FPGA Zynq 7 (1.8V@0.15A)

This reference design features multiple TPS54325 and other power devices for Xilinx Zynq FPGA. From 12-V input, this reference design has the power rails required by Zynq FPGA, including DDR3 memory.
Test report: PDF
Schematic: PDF
Package Pins Download
HTSSOP (PWP) 14 View options
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