#include #define EMIF 0x01800004 #define ADC_CONFIG 0x0140004C #define ADC_PGA 0x01400044 #define ADC_OFFSET 0x01400048 #define ADC_DATA 0x01400040 #define DMA_CTRL 0x01840000 #define DMA_CTRL2 0x01840008 #define DMA_SRC 0x01840010 #define DMA_DST 0x01840018 #define DMA_TCT 0x01840020 #define DMA_RELA 0x01840028 #define DMA_RELB 0x0184002C #define DMA_IDXA 0x01840030 #define DMA_IDXB 0x01840034 #define DMA_ADDA 0x01840038 #define DMA_ADDB 0x0184003C #define DESTINATION 0x8000C000 #define COUNT 16 #define BLOCK 256 #define COUNT_VALUE 0x00020000 #define DMA_CTRL_VALUE 0x4701c041 #define TIMER0_CTRL 0x1940000 #define TIMER0_PRD 0x1940004 #define TIMER0_COUNT 0x1940008 int data[1024]; main() { int i; CSR &= !1; for (i = 0; i < BLOCK; i++) data[i] = 0; *(int*) EMIF = 0x21e1c423; /*0x21e1c423*/ /* while (1) */ *(int*) ADC_PGA = 0x0007; *(int*) ADC_CONFIG = 0x0000; *(int*) ADC_OFFSET = 20; *(int*) DMA_RELA = COUNT_VALUE + COUNT; *(int*) DMA_TCT = COUNT_VALUE + COUNT; *(int*) DMA_ADDB = (int) data; *(int*) DMA_SRC = ADC_DATA; *(int*) DMA_DST = (int) data; *(int*) DMA_CTRL2 = 0x00000008; *(int*) DMA_CTRL = DMA_CTRL_VALUE; *(int*) ADC_CONFIG = 0x08F8; IER = 0x0103; CSR |= 1; while(1) { asm(" idle"); } } interrupt void dma0_handler(void) { static int iOffset = 0; static long i = 0; int iSample; i++; iOffset += COUNT * 4; if (i >= BLOCK/COUNT) { *(int*) ADC_CONFIG = 0x0000; for (i = 0; i < BLOCK; i++) { iSample = data[i] & 0x3FFF; if (iSample > 8191) iSample -= 16384; data[i] = iSample; } iOffset = 0; i = 0; /* *(int*) ADC_CONFIG = 0x0000; */ *(int*) ADC_CONFIG = 0x08F8; } *((int*) DMA_RELA) = COUNT_VALUE + COUNT; *((int*) DMA_TCT) = COUNT_VALUE + COUNT; *((int*) DMA_ADDB) = (int) data + iOffset; *((int*) DMA_SRC) = ADC_DATA; *((int*) DMA_DST) = (int) data + iOffset; *((int*) DMA_CTRL2) = 0x00000008; *((int*) DMA_CTRL) = DMA_CTRL_VALUE; }