INTRODUCTION At some point in every system designers career they are faced with the problem of synchronizing two digital signals operating at two different frequencies. This problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. However, this solution presents an awkward dilemma, the setup and hold time specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop used can influence overall system reliability. The purpose of this application report is to give the system designer a better understanding of the metastable characteristics pertaining to Texas Instruments Field Programmable Logic (FPL) Family. METASTABLE DEFINITION Whenever a flip-flops setup and hold time is violated, the flip-flops output response is uncertain. Presently, there is no circuit that can 100% guarantee its response. This is why the device manufacturer does not guarantee its operation. Specifically, the metastable state is defined as that time period when the output of a digital logic device is not at a logic level 1 (V out less than 2 V) or a logic level 0 (V out greater than 0.8 V), but instead between 0.8 V and 2 V. Since the input data is changing at the time of being clocked, the system designer does not care if the flip-flop goes to either a high or low logical level, just so long as the output does not hang up in the metastable region. The metastable characteristics for a particular flip-flop will determine how long the device stays in the metastable region. This concept is illustrated in the timing diagram of Figure 1. METASTABLE EVALUATION Any one who has tried to evaluate the metastable characteristics for a particular flip-flop has probably found it is not an easy task. The number of times the output hangs up in the metastable region is extremely small when compared to total number of clock transitions. In addition, the amount of time the output is actually in the metastable region is a variable and dependent on the type of device. From the design engineers viewpoint, when using a flip-flop as a data synchronizer, they can no longer use the specified data sheet maximum for propagation delay. Instead, to guarantee reliable system operation, they need to know how long after the specified data sheet maximum they need to wait before using the data. Conventional test equipment is not designed to measure these parameters, so a special test circuit is required for characterizing MTBF (Mean Time Between Failures) and trec (recovery time required after tco until Q valid). With these two parameters specified, the system designer can make a rational decision about what type of flip-flop to use, and how long to wait before using the data. Circuit Description þÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍþ The circuit in Figure 2 can be used in evaluating MTBF and dt for a selected flip-flop (DUT, Device Under Test). Two 'AS04s are used to detect whenever the Q output of the DUT is in the metastable region. This is accomplished by adjusting the input threshold to 2 V on one invertor and 0.8 V on the other. Notice that input thresholds are adjusted by referencing the ground input pins to 0.6 V and - 0.6 V, respectively. Therefore, whenever the Q output of the DUT is between 0.8 V and 2 V, the inserters will be in opposite states. Whenever the Q output of the DUT is higher than 2 V or lower than 0.8 V, both inserters will be at the same logic level. The outputs of the 'AS04s are then clocked (CP2) into two 'AS74s a selected time (tco + trec) after the DUT clock (CPI). The outputs of the 'AS74s are compared through an 'ALS86 and clocked (CP3) into another 'ALS74. This guarantees against any false clocking by the evaluation circuit. The output of the 'ALS74 is then fed to a series of three 'ALS160 counters, and on into three TIL31s for counter display. In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal must jitter around the threshold of the input clock. The width of the jitter should equal or exceed the setup and hold time specification for the device. In our evaluation circuit, this is accomplished by feeding a low level noise signal into the negative input of a TIL820 operational amplifier. It should be intuitively obvious that the worst-case condition for any specified input data frequency will be when the input data always violates the data setup and hold times. This condition is shown in the timing diagram of Figure 2. Any other relationship of CPI to DATA IN would provide less chance for the device to enter the metastable state. Therefore, it can be concluded that the worst-case condition for a given input data frequency will be 0.5 times the DUT clock rate where the input data always violates the setup and hold time. By using the described circuit, MTBF can be determined for several different values at trec. Plotting this information on semilog paper reveals the metastable characteristics for the selected flip-flop at the desired input data frequency. Test Circuit Limitations þÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍþ Before we proceed to the test results, it is important to analyze the limitations of our test circuit. In this way, we can better understand its effects on the test results. Two major areas which can greatly affect the test results are not centering the jitter around the input clock, and propagation delay of the 'AS04s. By not centering the jitter around the input clock, the risk of entering the metastable state is reduced. Proper care must be taken to ensure that the jitter is always centered around the input clock to guarantee worst-case conditions. The propagation delay of the 'AS04s affect the test results because they add propagation delay between the output of the DUT and the data being clocked into the 'AS74s. For example, the output on the DUT may come out of the metastable region, but the 'AS04s may not switch before CP2 occurs. This causes an inappropriate reading. The typical propagation delay of the 'AS04s, as configured in the test circuit, is approximately 4ns. This 4ns delay should be considered when evaluating the test results. If inserters slower than the 'AS04s are used in the test circuit, a larger offset must be considered. FPL Test Results þÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍþ Using the test circuit described in Figure 2, TI FPL device families were evaluated at several different dt time periods. The input clock frequency used was 1 MHZ with an input data frequency of 500 kHz. The devices were allowed to run until an appropriate amount of errors were recorded. The number of errors were then divided by the total time the devices were allowed to run. This results in a MTBF for the selected trec. The W, Tsw constants were calculated as shown below. The average characteristics for all FPL products are shown in Table 1. The 4ns offset generated by the test circuit is not subtracted from the data. Other Clock Frequencies þÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍþ Clock frequencies other than 1 MHz will either increase or decrease the probability of the device entering the metastable state. The faster the frequency, the higher the probability of entering the metastable state. Likewise, the slower the frequency, the lower the probability of entering the metastable state. From the data taken in the above experiment, an equation can be derived for the metastable characteristics at other clock frequencies. Equation (1) relates input clock and data frequency to metastable characteristics. Metastable Equation e(trec/Tsw) MTBF = þÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄþ (1) fcp * fdata * W As stated earlier, the worst situation for the test circuit shown in Figure 2 is when the data setup and hold time is always violated. Based on this assumption, the equation is reduced to the following. 2 e(trec/Tsw) (2) MTBF = þÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄþ fcp2 * W The constants W and Tsw describe the metastable characteristics of the device. From the experimental data graphed in Table 1, these constants can be solved for each device family. As an example, the constants are solved below for the 5ns device family. Tsw is defined by the slope of the line reciprocated. Picking two data points off the graph yields the following: 10.13 - 5.55 10.13 - 5.55 Tsw = þÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄþ = þÄÄÄÄÄÄÄÄÄÄÄÄÄþ = 0.498 ln 103 - ln 10-1 ln 10 (3 - -1) By plugging Tsw into equation 2, along with using one of the data points off the graph, W can be solved for: 2 e(trec/Tsw) (2) MTBF = þÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄþ fcp2 * W 2 e(5.55/.498) 10-1 = þÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄþ (106)2 * W W = 1.43 * 10-6 Inserting W and Tsw into equation 2, yields the metastable equation for -5ns PLD. e (trec/.498) MTBF = þÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄþ 1.43 * 10-6 fcp * fdata Given this worst-cast equation, the system designer can determine the metastable characteristics for the -5ns PLD when using other input clock frequencies. The equations for other PLDs can be derived using the same procedure. Their constants are in the following table. Table 1. Texas Instruments PLD Metastability Characteristic Constants 10-YEAR 10-YEAR MTBF MTBF DEVICE W(s) Tsw(ns) Trec(ns) Fmax(MHz) ÄÄÄÄÄÄÄÄÄÄÄÄþ þÄÄÄÄÄÄþ þÄÄÄÄÄÄþ þÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄþ TIBPAL16R8-5 1.43E-06 4.98E-01 15.33 42.87 TIBPAL16R8-7 1.89E-10 1.78E+00 38.92 18.72 TIBPAL16R8-10 8.15E-11 1.50E+00 31.46 19.06 TIBPAL16R8-15 2.18E-10 1.08E+00 23.77 22.34 TIBPAL16R8-25 7.34E-09 1.50E+00 38.30 13.64 TIBPAL22V10A 1.68E-10 1.92E+00 41.74 13.03 TIBPAL22V10-15 1.17E-11 1.06E+00 20.15 22.15 TIBPLS506A (OUTPUT) 1.83E-10 1.83E+00 39.94 15.40 TIBPLS506A (INTERNAL) 1.87E-09 1.23E+00 29.68 18.29 TIBPLS507A (OUTPUT) 1.98E-10 1.74E+00 38.05 16.65 TIBPLS507A (INTERNAL) 6.86E-09 1.18E+00 30.00 19.23 TICPAL22V10Z(T) 2.15E-11 3.21E-01 6.31 24.21 TICPAL22V10Z (ZP) 5.38E-12 2.61E-01 4.77 20.94 TICPAL16R8-55 1.87E-09 8.25E-01 19.88 12.21 EP330 4.44E-05 3.35E-01 11.44 28.22 EP630 7.16E-11 3.41E-01 7.10 23.75 As a general rule, a system designer can usually get a feel for the metastable characteristics of a device by simply looking at the setup and hold-time specifications. Usually, the smaller the setup and hold time numbers, the better its metastable characteristics will be. However, in the case of programmable logic, the setup and hold-time numbers are not reflective of metastable characteristics. This is because the setup and hold time numbers also reflect the propagation delay time of the AND/OR logic in front of the flip-flops. SUMMARY The metastable characteristics of a flip-flop used for data synchronization can greatly affect system reliability. Based on the information presented in this application report, the system designer can make a rational decision about what type of flip-flop to use and what its metastable characteristics will be. It is easy to see from the experimental data shown in Table 1, that the -5 offers the best metastable characteristics. It has a much narrower setup and hold time window, and is quicker to recover once it gets into the metastable region. However, with adequate sampling time, CMOS and EPLDs will also perform well. The selection of what type of flip-flop to use must be based on the speed of the application. As a general rule, the faster the flip-flop the better its metastable characteristics. We at Texas Instruments believe that the graphs shown and equations derived represent a reasonable assumption about the metastable characteristics for the device families discussed. However, we strongly recommend that when using flip-flops as data synchronizers, an adequate amount of guardband is allowed between the characteristics shown and when the output of the flip-flop is actually sampled.