TI DDR (Double Data Rate) DIMM Applications

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   Digital Logic DDR (Double Data Rate) DIMM

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Texas Instruments offers a variety of solutions for Registered Double Data Rate (DDR) DIMM applications. Our SN74SSTV16857 is a 14-bit 1:1 register with low-power mode support while the SN74SSTV16859 is a 13-bit to 26-bit 1:2 register with low-power mode support.
The SN74SSTV32852, 24-bit to 48-bit registered buffer is the best solution for stacked, double sided, 1U low-profile DIMMs. Available in the 114-ball LFBGA, this device is ideal for 1U DIMM where board real estate is at a minimum. Best of all, the SSTV32852 is a one chip, BGA solution which presents a cost advantage and increases manufacturability over the competition.
The CDCV857 differential clock completes the TI solution for 184-pin DDR SDRAM modules. For product datasheets, samples, simulation models, and other support tools click on any of the device links found on this page.

Recommended Registered Buffers

DIMM Configuration PC-1600/2100
DDR-200/266
JEDEC Standard PC-1600/2100
DDR-200/266
Low-Profile (1U) PC-2400/2700
DDR-300/333
Low-Profile (1U)

Planar
1-bank x8 SDRAMs
9 loads two SN74SSTV16857 one SN74SSTV32867 one SN74SSTV32867

Planar double-sided
2-bank x8 SDRAMs
1-bank x4 SDRAMs
18 loads two SN74SSTV16857 two SN74SSTV16857 two SN74SSTV16859

Stacked double-sided
1-bank x4 SDRAMs
36 loads two SN74SSTV16859 one SN74SSTV32852 In Development

Registers

SN74SSTV16857 SN74SSTV16859 SN74SSTV32852 SN74SSTV32867 SN74SSTV32877

Function 1 to 1 register 1 to 2 register 1 to 2 register 1 to 1 register 1 to 1 register

Bit Width 14-bit 13-bit 24-bit 26-bit 26-bit

V_CC 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V

/OE No No No No Yes

SSTL_2 Input Yes Yes Yes Yes Yes

Output SSTL 2 SSTL 2 SSTL 2 ULTTL SSTL 2

JEDEC Specification JC40 Item 6 JC40 Item 32 JC40 Item 60 JC40 Item 57.1 JC40 Item 57.2

Sample Availability Released TBD Engineering Samples Available Now Sampling Now Sampling Now

Clock Drivers

CDCV857B CDCV857/A CDC857-2

JEDEC Specification JESD79 JESD79 Not JEDEC Compliant

Comments Supports low-power modes Supports low-power modes Does not support low-power modes

+/- 50 ps static phase offset for DDR333 +/- 75 ps static phase offset for DDR 200/266

Application Reports
SSTL for DIMM applications
Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 DDR-DIMM Registers
TL5002 Provides DDR Bus Termination Power Supply Solution