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Computer Memory
Architecture
> DDR Clocking Solution
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This is preliminary data; parameters are subject to change. Devices will be available Quarter 3, 2000. Contact your local TI sales representative for samples.
CDCV857
- Phase-Lock Loop clock driver for DDR synchronous DRAM applications
- Operating frequency: 60 to 170 MHz
- Operates from a 2.5-V supply
- Cycle-to-cycle jitter < |75| ps
- Ultralow-power-down mode: <100uA
- Spread Spectrum EMI reduction mode
- Optimized to work with CDC950 and CDCV850
- 48-Pin TSSOP package
CDC950
- Differential clock synthesizer/driver for PC motherboards
- Operating frequency: 100 or 133 MHz
- Optimized to work with the CDCV850 and CDCV857
- Operates from a single 3.3-V supply
- Spread Spectrum EMI reduction mode.
- 48-Pin TSSOP package
CDCV850
- Phase-Lock Loop clock driver for PC motherboards
- Two-line serial interface
- Operating Frequency: 60 to 170 MHz
- Optimized to work with CDC950 and CDCV857
- Operates from dual 2.5-V and 3.3-V supplies
- Cycle-to-cycle jitter < |75| ps
- Ultralow-power-down mode: <100uA
- Spread Spectrum EMI reduction mode
- 48-Pin TSSOP package
CDCV304
- General-purpose and PCI-X 1:4 clock buffer
- Operating frequency: 0 to 140 MHz
- Operates from a 3.3-V supply
- 8-Pin TSSOP package
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