High-Speed Data Acquisition and Generation

Block Diagram (SBD) for a high-speed data acquisition front-end solution utilizing high-speed ADCs and DACs, amplifiers, and TI DSPs to capture, analyze and generate high-speed analog signals

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High Speed Data Acquisition System

A high speed data acquisition system implements high-speed integrated circuits to trigger and acquire high data rate flow control and storing.

Core Subsystems include:

Analog Input Front End - built around a high-speed ADC including high-speed Op-Amps, FIFOs, and SRAMs. The stream of data output from the ADC is written into FIFOs, stored in blocks of SRAM, and sent directly to the outside world through registers under the control of the data acquisition logic in the FPGA.
FPGA - contains data acquisition controls and logics including the trigger logic, error detection, DSP interface, memory address decoder, counters, and output control. The control logic selects a data acquisition clock, processes different triggers, and transfers the acquired data to the internal memory of the data acquisition channels.
Analog Output - built around a high-speed DAC, including Op-Amp and output data buffer.
High-Speed Bus Interface - transfers data through high-speed parallel bus on the back plane (PCI,VMEbus) or high-speed Ethernet.
Clock Source - provides clock for different data acquisition options and modes.
Power Managements - converts the input power from the backplane to run various functional blocks.

Title	Abstract	Type	Size (KB)	Date	Views
A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)		PDF	425 KB	09 Oct 2011	5242
EEPROM Emulation With the TMS320F28xxx DSCs	Read Abstract	HTM	9 KB	21 Sep 2009	3635
Flash Programming Solutions for the TMS320F28xxx DSCs	Read Abstract	HTM	8 KB	19 Aug 2008	4669

Title	Abstract	Type	Size (KB)	Date	Views
2010 Clocks and Timing Selection Guide (Rev. C)		PDF	794 KB	27 Oct 2010	2989

Name	Part #	Company	Software/Tool Type
Anti-Aliasing Calculation Tool for A to D Converters	ANTIALIASINGCALC	Texas Instruments	Calculation Utilities
Code Composer Studio (CCStudio) Integrated Development Environment (IDE) v5	CCSTUDIO	Texas Instruments	Code Composer Studio(TM) IDE
Op Amp to ADC Circuit Topology Calculator	ADC-INPUT-CALC	Texas Instruments	Calculation Utilities

Title	Abstract	Type	Size (MB)	Date	Views
TMS320C6671/72/74/78 High-Performance Multicore Fixed- and Floating-Point DSPs (Rev. B)		PDF	208 KB	25 Apr 2011	3030

Title	Abstract	Type	Size (MB)	Date	Views
An overview of TI's Multicore Software Development Kit (Rev. A)		PDF	1014 KB	17 May 2011	2840

Direct RF Sampling with High Performance ADC - Philip Pratt , ECNmag.com
01 Sep 2008 View Article
ADCs: Does ENOB tell the whole story? - Bonnie Baker , EDN
17 Apr 2008 View Article
Programmability offers versatility in high-speed ADCs - Phillip Pratt, Systems Engineer , Planet Analog
24 Oct 2007 View Article

Name	Type	Available During
TI's C553x DSPs - industry's lowest price and lowest power DSPs TI's breakthrough price for DSPS extends sophisticated signal processing and ultra-low-power into new world of cost-sensitive apps	On-Line Training	On Demand
Multicore Software Development Kit (MCSDK) Online Training This self-paced training course provides an introduction to the various components that make up the C66x KeyStone devices.	On-Line Training	On Demand
Texas Instruments' Training Lab - ARM Tech Conference 2010 This self-paced training course provides an introduction to the various components that make up the C66x KeyStone devices.	On-Line Training	On Demand
C66x Multicore SOC Online Training for KeyStone Devices This self-paced training course provides an introduction to the various components that make up the C66x KeyStone devices	On-Line Training	On Demand
High-Speed Board-Design Considerations for OMAP™ Applications The OMAP35x BGA package was designed to simplify board layout.	On-Line Training	On Demand