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Iris Biometrics

Iris Biometric Solutions from Texas Instruments.

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Design Considerations

Iris Recognition Biometric Solutions from Texas Instruments

Iris Recognition Biometrics are used in applications requiring fast, secure and convenient user identification including online transactions, law enforcement, time and attendance monitoring, and access control. Digital signal processing elements in iris scanners perform complex DSP functions such as filters, transforms, feature extraction, matching operations and other algorithms.

Iris sensors use optical technologies to obtain an image of an iris’ features. The most common iris sensor solution first illuminates the eye with infrared light and then captures the image using a CCD or less expensive CMOS sensor. Iris sensors are typically self contained modules that include an analog to digital converter to translate the analog information into a digital data stream. Resolution, dynamic range and pixel density are factors that contribute to the image quality and influence the accuracy of the sensor.

Once the image is captured the digital information is transferred to a digital signal processor to generate a match. The first step in the matching process is conditioning the scanned image. Iris readers rarely use the full iris image for identification. Rather, DSPs use algorithms to extract the unique features and patterns of each iris to generate a unique digital code. The second step in the software flow is to take the code generated from the scanned image and compare it to a database of potential matches. The compare step requires the system to have access to information in a networked database or a non-volatile memory unit.

The need for real-time data collection to allow fast pattern matching makes the C674x DSP a compelling solution for this application.

  • The floating-point and fixed-point performance of the core meet the processing power and image algorithm requirements for iris detection and recognition.
  • The support for SRAM, SDRAM, DDR2, mDDR, NAND Flash, and NOR Flash as well as a 64 channel DMA and integrated 10/100 EMAC allow access to existing user databases.
  • Optional secure boot and JTAG disable as well as optimized cryptography libraries provide protection of proprietary algorithms and sensitive user data.
  • On-chip LCD controller supports up to XGA (1024X768) resolution for graphical display of result notification.

Application Notes (2)

Title Abstract Type Size (KB) Date Views
HTM 9 KB 19 Dec 2011 725
HTM 8 KB 06 Oct 2011 3756
    

Product Bulletin & White Papers

White Papers (1)

Title Abstract Type Size (MB) Date Views
PDF 2.01 MB 30 May 2012 3422

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