Video Broadcasting & Infrastructure: Scalable Platform

Video Broadcasting & Infrastructure Solutions from Texas Instruments

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AC/DC Adaptor

Design Considerations

This professional studio-quality video encoding and decoding broadcast scalable platform leverages the processing power of the TMS320C6474 multi-core DSP and the flexibility of the TMS320DM6467 Digital Media SoC to render a truly unique system that can be adjusted to suit the capability of the end product. In this system, the ‘C6474 is used as the codec processor for the 4:2:2 video input. As this block diagram represents the receiving end of the video broadcasting studio end equipment, the GC5325 processor is used extensively in the transmission side of video equipment to send digital data via a fiber optic cable or radio link. An EVM (called the GC5325SEK), which includes a TSW3100 Digital Pattern Generator, is available for this wideband digital predistortion transmit processor.

TMS320C6474 Functionality:

  • In encode mode, raw video is fed via the VPIF/SRIO interface. One of the cores on the daughter card will act as a master and manage all encoding tasks on other C6474 chips/cores.
  • In decode mode, bit streams are fed via the GbE interface; decoded raw video will be sent to the DM6467 for post processing (scaling, etc).
  • Coding tasks can be partitioned via either slicing or functional partition across all 9 cores on the three C6474 DSPs.

Encoder Features:

  • Live MPEG-4, H.264, AVS and WMV9 encoding
  • High-end video compression algorithms, such as H.264 live encoding of synchronized video and audio
  • High-quality and performance with full D1 video and audio code-compatible (AAC)

Decoder Features:

  • Decode either MPEG-2 MP@HL or MPEG-4 AVC (H.264) HP
  • The DM6467 digital media processor can be programmed to support a number of audio and video standards and can be updated easily through software as network configurations and service needs change.
  • The DM6467 combines the DSP with HD video and imaging coprocessors to provide the high-speed computation required for HD video decoding, plus an ARM926 RISC processor for user interfaces, system control and programming ease.

The Core Subsystem Includes:

  • 1080i Analog video input and output
  • HD-SDI input and output
  • AES3 / S/PDIF digital audio input and output
  • Analog audio input and output
  • IP GbE communication
  • Transmission of decoded signal to an HD display for viewing or monitoring in real time
  • For added flexibility, additional high-performance daughtercards for 4:2:2 video processing can be utilized for multi-channel operations.

Application Notes (7)

Title Abstract Type Size (KB) Date Views
HTM 9 KB 14 Oct 2008 92
HTM 9 KB 14 Oct 2008 70
HTM 8 KB 14 Oct 2008 77
HTM 8 KB 30 Sep 2008 58
HTM 8 KB 10 Sep 2008 58
HTM 8 KB 05 May 2008 429
HTM 8 KB 20 Oct 2005 278
    

Reference Designs

Selection and Solution Guides

Selection Guides (2)

Title Abstract Type Size (KB) Date Views
PDF 5.57 MB 12 Aug 2014 6810
PDF 2.55 MB 10 Oct 2013 3864

Product Bulletin & White Papers

Product Bulletin (5)

Title Abstract Type Size (MB) Date Views
PDF 245 KB 22 Jan 2013 1189
PDF 199 KB 09 Nov 2012 297
PDF 426 KB 11 Apr 2012 717
PDF 228 KB 09 Jun 2011 367
PDF 208 KB 25 Apr 2011 644

White Papers (19)

Title Abstract Type Size (MB) Date Views
PDF 202 KB 21 Feb 2013 1039
PDF 207 KB 06 Feb 2013 1523
PDF 1.09 MB 12 Nov 2012 458
PDF 652 KB 09 Oct 2012 408
PDF 284 KB 29 Mar 2012 148
PDF 667 KB 05 Mar 2012 1377
PDF 914 KB 23 Feb 2012 255
PDF 130 KB 29 Nov 2011 178
PDF 1014 KB 17 May 2011 763
PDF 552 KB 25 Apr 2011 199
PDF 562 KB 21 Dec 2010 440
PDF 423 KB 09 Nov 2010 514
HTM 9 KB 15 Feb 2010 134
HTM 9 KB 15 Feb 2010 151
PDF 166 KB 20 Jan 2010 123
PDF 180 KB 26 Oct 2009 249
PDF 150 KB 28 Aug 2009 594
HTM 8 KB 14 Oct 2008 81
PDF 72 KB 18 Aug 2008 4

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