Other Parts Discussed in Thread: AFE7950
Hi,
I am using AFE7900 and AFE7950 EVM. I want to know whether AFE7900/AFE7950 only supports the output sample rate(interface rate) mentioned in Table 8-5 below? or we can handle any sample…
Hi TI experts, I'm currently using the JESD IP provided by TI on the Zynq UltraScale+. I've configured it with 2 lanes and set the LMFSHd parameters in the Latte script to 22210. I've attached…
Hi,
Greetings!
We are planning to integrate four AFE7906 with AMD's versal premium VP2802 SoC with the following configuration.
Sampling Rate: upto 3GSPS
Number of channels: 6
Bandwidth Required: 500Mhz.
In VP2802 SoC, I am planning…
Hi
I read the thread for TI-JESD204-IP release
Hi,
I will use ZCU102 evaluation board with DAC37J84. I intend to use the ip core JESD204 from the xilinx vivado software. Can I use IP Core JESD204B from the supplier xilinx and not from…
Hi,
I will use ZCU102 evaluation board with ADS54J60EVM. I intend to use the ip core JESD204 from the xilinx vivado software. Can I use IP Core JESD204B from the supplier xilinx and not…
DAC38RF82 The SYNC signal is high when it is powered on
I encountered a problem when debugging the DAC38RF82, as soon as the chip was powered on, it remained high without JESD204B link…
The FPGA and ADC1 (AFE7906) and ADC2 (AFE7906) are connected.
I would like to configure the MUX as shown in Figure 1.
Output ADC input data of ADC1_1RX to ADC1_Lane1(3stx)
Output ADC input data of ADC1_2RX to ADC1_Lane2(4stx)
Output…
Hello,
We are testing AFE7900EVM board with Xilinx ZCU102 together,
using the design files that are included in 'ZCU102_AFE79xx_8b10b_10Gbps' folder in TI JESD204 IP reference designs.…
>Could you check that you are getting the Bytes correctly from your IP core?
>We have see other IP cores where there was a need to swap the Bytes
The IP core uses JESD204C from AMD's Vivado Design Suite
Is there any precedent…
It seems that the Ramp test now works by configuring the following settings after "AFE.deviceBringup()".
Data15:8 and Data7:0 look reversed
Is this normal behavior?
### ADC Test Patterns
mode=2
# 0 - No Test Pattern
# 1 -…
I am using AFE7906, but the test pattern is like the evaluation between JESD204B TX side and FPGA.
I would like to issue a test pattern, but are there any test patterns other than PRBS?
1. PRBS9 (x9 + x5 + 1).
2. PRBS15 (x15 + x14 …
Hi, im currently working with the DAC38RF82EVM and I need to send the SYNC pulse from the DAC to an FPGA using one of the GPO ports.
I found that the levels at the output of the GPO ports are not 1.8V, im measuring 2.7V instead…
Hi, I am using the TI IP on a Kintex Ultrascale Board with AFE7950. The problem I am facing is that no data is shown on the ILA of the TI IP after I run the Ramp Test Pattern on Latte. The…
Dear Team,
We’re working on FPGA, and will need some help with getting started. If you can provide frame structure / K codes any other material which can help us understand requirement to interface board it’d be great.…
Hello,
Currently I try to connect SYSREF+/- differenctial pair of LMK04828 to that of ADC09DJ1300.
I am thinking of using DC coupling of LVPECL interface because of JESD204B interface…
Hello, I am try to understand Dynamic Reconfiguration Lane Rate for TI-JESD204-IP.
Does this feature supported? And does any reference example ?
Thanks
Daniel
Hi Ti-Team,
I am testing the Xlinx JESD204-IP for interfacing the AFE7950EVM.
My evaluation board is zcu102 and I connect afe7950evm to the HPC1 of zcu102. I am trying to use 8b/10b in the mode of subclass 1.
I didn't almost change…