The ADS54J54 EVM demonstrates the performance of a quad 500Msps 14 bit ADC with the JESD204B interface. It includes the ADS54J54 device and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for each channel of the ADC is by default connected to a transformer input circuit which can be connected to a 50 ohm single ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50 ohm single ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks. Register access is provided through the on board USB connection and a GUI. An industry standard JESD204B pin assignment on a FMC connector allows direct connection to the TSW14J56 Capture Card as well as many commercially available FPGA development platforms.
| Type | Title | Date | ||
|---|---|---|---|---|
| Certificate | ADS54J54EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| EVM User's guide | ADS54J54 EVM Users Guide (Rev. A) | 08 Jan 2016 | ||
| User guide | Pipeline ADC Code Error Rate Analysis and Measurement | 03 Nov 2015 | ||
| Design guide | ADS58J89, ADS54J54EVM Design Package (Rev. A) | 10 Jul 2015 |
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