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TIDA-00467

Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design

Design files

TIDA-00467

Design files

Overview

A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the
sampled data from the ADCs are phase aligned.

Features
  • Synchronized 2 giga sample ADCs sampling at 3.072GHz
  • System expandable to more than 2 ADCs
  • Phase variation less than 1 ADC clock period
  • Easy to use software interface for control and data acquisition
  • Excellent spur and noise perfromance of ADC at 3.072GHz
  • This design is tested and includes software, demo hardware and a design guide.
Industrial
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

download Design guide — TIDA-00467
TIDU851.PDF (603 K)

Reference design overview and verified performance test data

download Schematic — TIDA-00467
TIDRE83.PDF (1278 K)

Detailed schematic diagram for design layout and components

download Schematic — TIDA-00467
TIDRE84.PDF (250 K)

Detailed schematic diagram for design layout and components

download Bill of materials (BOM) — TIDA-00467
TIDRE85.PDF (318 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

download Bill of materials (BOM) — TIDA-00467
TIDRE86.PDF (216 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

download Assembly drawing — TIDA-00467
TIDRE87.PDF (1261 K)

Detailed overview of design layout for component placement

download Assembly drawing — TIDA-00467
TIDRE88.PDF (117 K)

Detailed overview of design layout for component placement

download CAD/CAE symbol — TIDA-00467
TIDRE90.ZIP (9933 K)

Files used for 3D models or 2D drawings of IC components

download Gerber file — TIDA-00467
TIDCA48.ZIP (712 K)

Design file that contains information on physical board layer of design PCB

download Gerber file — TIDA-00467
TIDCA49.ZIP (1436 K)

Design file that contains information on physical board layer of design PCB

download PCB layout — TIDA-00467
TIDRE89.PDF (2955 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

High-speed ADCs (≥10 MSPS)

ADC12J4000 — 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML

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Software

Technical documentation

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Type Title Date
Design guide Synchronizing Multiple JESD204B ADCs for Emitter Position Location Design Guide Mar. 24, 2015

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