Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers TIDA-010131 (ACTIVE)
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- Multichannel RF transceiver clocking reference design for RADARs and wireless 5G
(PDF 7688 KB)
27 Feb 2019
Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and a clock subsystem. The clock subsystem provides low noise sampling clocks with precise delay adjustment to achieve lowest channel-to-channel skew and optimum system performance like signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), IMD3, effective number of bits (ENOB), and so forth. This reference design demonstrates multichannel JESD204B clocks generation and system performance with AFE7444 EVMs. Channel-to-channel skew better than 10 ps achieved with 6 GSPS/3 GSPS DAC/ADC clocks up to 2.6-GHz radio frequencies and system performance like SNR and SFDR are comparable to the AFE7444 data sheet specifications.
- JESD204B complaint clock solution for 8T8R RF sampling analog front end
- Digital functions synchronization across multiple RF AFE transceivers
- Low phase noise clock generation for 14-bit, RF sampling AFEs
- Fine phase delay adjustment in steps of approximately 500 fs to achieve phase synchronization across multiple devices
- Supports high-speed data converters and capture cards (AFE7444EVM, TSW14J56EVM, TSW14J57EVM)