CDCLVP111-SP 1:10 LVPECL Clock Driver Evaluation Module


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The CDCLVP111-SP EVM allows testing and validation of the CDCLVP111 clock distribution buffer utilizing a ceramic Engineering Model (EM).

  • Distributes one of two differential input clocks to 10 differential LVPECL output clocks
  • Clock input selectable
  • Low output skew
  • Wide supply range

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CDCLVP111-SP 1:10 LVPECL Clock Driver Evaluation Module



TI's Standard Terms and Conditions for Evaluation Modules apply.

Technical Documents
User guides (1)
Title Abstract Type Size (KB) Date Views TI Recommends
PDF 641 17 Nov 2016 128

TI Devices (1)

Part Number Name Product Family
CDCLVP111-SP  1:10 High Speed Clock Buffer with Selectable Input Clock Driver  Clock & Timing Products 

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