TI does not offer ongoing direct design support for this hardware. For support while working through your design, contact Dallas Logic Corporation.
DEV-ADC34J22
Overview
The DEV-ADC34J22 is a four-channel, 50MSPS ADC Module designed to integrate with Altera’s HSMC standard. The DEV-ADC34J22 features TI’s new JESD204B compliant ADC34J22 Analog Digital Converter (ADC), with clocking conditioning using TI’s LMK04828 jitter cleaner. It provides single-ended DC coupled inputs on two of the four channels through TI’s THS4541 850MHz BW fully differential amplifier.
The module offers six front panel SMA connectors: 1 EXT trigger, 1 EXT clock and 4 Analog Input Channels, and an on board 10MHz TCXO for stand -alone clock generation, with a 100MHz VCXO used in conjunction with the LMK04828B for reference clock jitter cleaning. The ADC34J22 and the LMK04828B are completely configurable via Altera’s Cyclone V SOC FPGA with embedded ARM Cortex A9 processors. The DEV-ADC34J22 supports a wide range of applications and offers two RF (AC coupled) channels and two Analog (DC coupled) channels.
Features
Board Features
- Texas Instruments ADC34J22 Analog to Digital Converter
- 4 channel, 12bit, 50 MSPS, JESD204B compliant ADC module
- Two RF AC coupled input channels
- Two Analog DC coupled input channels
- External clock input
- External trigger input
- On board TI LMK04828B Dual Loop
- Clock Jitter Cleaner Reference oscillator - 10MHz. TCXO
- 1st Loop VCO - 100MHz. VCXO
- HSMC connector for interfacing with Altera FPGA development boards
- Supports up to four JESD204B lanes
- JESD204B Sub-class 0 & 1 compatible
- SPI control interfaces for both the ADC34J22 and LMK04828B devices
- Reference design available for Arrow’s SOCkit development board
- VHDL design files including MTI’s JESD core instantiation
- Module is configured at power-up by the SOC’s ARM processor
AC Coupled RF Front End Features
- Transformer coupled single ended to differential conversion
- Available on Channels 1 & 2
- RF Front End Specifications: Input range +/- 1.0V (2V p-p)
- 0.5 - 200 MHz input bandwidth
Two Analog DC Coupled Input Channels
- Single Ended to Differential Amplifier with G=2 V/V Available on Channels 3 & 4
- Analog Front End Specifications:
- Input range +/- 0.5 V i.e. 1 Vp-p
- DC - 15 MHz input bandwidth
High-speed ADCs (≥10 MSPS)
Clock jitter cleaners & synchronizers
Fully differential amplifiers
Photos courtesy of Dallas Logic Corporation
Order & start development
Evaluation board
DEV-ADC34J22 — DEV-ADC34J22 4-channel 50MSPS ADC Evaluation Module
Support & training
Video series
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