LMK04906BEVAL

Three Input, Seven Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VCO

LMK04906BEVAL

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Overview

The LMK04906 is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

Features
  • Multi-mode: Dual PLL, single PLL, and clock distribution
  • Dual Loop PLLatinum PLL Architecture
    • PLL1
      • Automatic or manual triggering/recovery
    • PLL2
      • Integrated Low-Noise VCO
  • 3 redundant input clocks with LOS
    • Automatic and manual switch-over modes
  • 50% duty cycle output divides, 1 to 1045 (even and odd)
  • LVPECL, LVDS, or LVCMOS programmable outputs
  • Precision digital delay, fixed or dynamically adjustable
  • 25 ps step analog delay control.
  • 13 differential outputs. Up to 26 single ended.
    • Up to 6 VCXO/Crystal buffered outputs
  • 0-delay mode
Clock jitter cleaners
LMK04906 Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
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Evaluation board

LMK04906BEVAL/NOPB — Three Input, Seven Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VCO

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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

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TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

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Latest version
Version: 1.7.7.5
Release date: 23 Jul 2024
lock TICSPro_1.7.7.5_23-Jul-2024.exe  — 142660 K

TICS Pro 1.7.7.5 installer binary for Windows operating system

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Documentation

TICS Pro 1.7.7.5 Release Notes

TICS Pro 1.7.7.5 Software Manifest

Release Infomation

Added Features

  • LMK5B12212, LMK5C22212A support EEPROM programming

Bug Fixes

  • LMK3H0102 - No longer writes registers on startup.
  • LMK05318B - Export EEPROM Map button bugfix.
  • LMK5B/LMK5C family - Small usability bug-fixes.

Known Issues

  • LMK5C33216
    • When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
  • LMK05318
    • In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
  • Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
  • User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.

What's new

  • Bugfixes and improvements.
TI's Standard Terms and Conditions for Evaluation Items apply.

Technical documentation

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Type Title Date
* EVM User's guide LMK04906 Evaluation Board User's Guide (Rev. A) 26 Nov 2013
Certificate LMK04906BEVAL/NOPB EU Declaration of Conformity (DoC) 02 Jan 2019

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