The PMP10520 reference design provides all the power supply rails (1V/20A, 1.2V/30A, 1.8V/4A) necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Virtex® Ultrascale™ FPGAs. This design uses a 5V input and has a PMBus interface for current and voltage monitoring, margining, timing delays, and fault monitoring. It uses both TPS544C20 and TPS544B20 which feature internal current sensing and eliminate the need for an external current sense resistor. This design also meets Xilinx's low output voltage ripple requirements of the MGT rails.
| Output voltage options | PMP10520.1 | PMP10520.2 | PMP10520.3 |
|---|---|---|---|
| Vin (Min) (V) | 4.5 | 4.5 | 4.5 |
| Vin (Max) (V) | 5.5 | 5.5 | 5.5 |
| Vout (Nom) (V) | 1 | 1.2 | 1.8 |
| Iout (Max) (A) | 20 | 30 | 4 |
| Output Power (W) | 20 | 36 | 7.2 |
| Isolated/Non-Isolated | Non-Isolated | Non-Isolated | Non-Isolated |
| Input Type | DC | DC | DC |
| Topology | Buck- Integrated Switch^Buck- Synchronous | Buck- Integrated Switch^Buck- Synchronous | Buck- Synchronous |
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Test results for the reference design, including efficiency graphs, test prerequisites and more
Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| Test report | PMP10520 Overview | Nov. 18, 2014 | ||
| Test report | PMP10520 Test Results | Sep. 25, 2014 |
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