This reference design generates a 5V/10A output from a standard telecom 48V DC input. The UCC2897A controls an active clamp forward converter power stage. The low gate charge and low RDSon of the CSD17309Q3 and CSD18540Q5B, implemented as self-driven synchronous rectifiers, allow this design to achieve a max load efficiency over 93%. This design uses only ceramic output capacitors for high reliability and uses 100% surface mount components. The board is laid out on a standard eighth brick footprint.
| Output voltage options | PMP9108.1 |
|---|---|
| Vin (Min) (V) | 36 |
| Vin (Max) (V) | 75 |
| Vout (Nom) (V) | 5 |
| Iout (Max) (A) | 10 |
| Output Power (W) | 50 |
| Isolated/Non-Isolated | Isolated |
| Input Type | DC |
| Topology | Forward- Active Clamp^Forward- Synchronous |
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| Test report | PMP9108 Test Results | Sep. 10, 2014 |
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