Description

SDALTEVK is a triple-rate SDI and video clocking daughter card for the Altera Cyclone III development kit. The kit provides broadcast video system designers a comprehensive platform for rapid evaluation and prototyping of new designs to reduce time to market. TI's daughter card, SDALTEVK, includes synthesizable FPGA source code available in both Verilog and VHDL to maximize flexibility and facilitate IP customization. The daughter card plugs directly into the Altera Cyclone III development board via Altera's high-speed mezzanine connector (HSMC).

The SDALTEVK kit consists of:

• TI's HSMC SDI video and clocking daughter card (SDALTEVK)
• Comprehensive user manual, schematics, and bill of materials (BOM)
• FPGA IP (not included in box)

To maximize flexibility and facilitate IP customization, Texas Instruments provides synthesizable FPGA source code in both Verilog and VHDL formats.

SDALTEVK Hardware Description

The SDALTEVK daughter card contains:

• LMH0344 - Triple-rate SDI Adaptive Cable Equalizer
• LMH0340 - Triple-rate SDI Serializer with integrated cable driver
• LMH0341 - Triple-rate SDI deserializer with reclocked loop through
• LMH1981 - Multi-Format Video Sync Separator
• LMH1982 - Multi-Rate Video Clock Generator
• DS90CP22 - 2x2 LVDS Crosspoint Switch
• LP3878-ADJ - Adjustable Low Noise LDO
• LM20242 - PowerWise Buck Regulator

The SDALTEVK supports a complete 3G-SDI signal path consisting of adaptive cable equalizer (LMH0344), deserializer with reclocked loop through (LMH0341) and serializer with integrated cable driver (LMH0340). A multi-rate sync separator (LMH1981) and clock generator (LMH1982) deliver ultra-low jitter reference clocks to the host FPGA. A 2x2 LVDS crosspoint switch (DS90CP22) acts as a reference clock selector to choose between four separate clocking options:

• Recovered clock from LMH0341 deserializer
• Genlock from analog reference, LMH1981 sync separator and LMH1982 clock generator
• Local clock generation from LMH1982 in free-run mode
• External clock via SMA connector

These selectable reference clocks allow designers to compare system performance using different clocking sources. For example, one application may require genlock capability for synchronization while another one leverages the recovered clock from the SDI deserializer. Designers may compare system jitter performance of each clocking solution then make architectural decisions based on system requirements and constraints.

FPGA IP Description

A full set of FPGA firmware is available from TI as source code to enable quick system integration and faster time to market. This IP implements the SMPTE SDI protocol processing blocks. A reference design using this IP is available for the Cyclone III 3C120 host development kit and is compatible with other Cyclone III devices, including the Cyclone III 3C25.

The IP architecture includes:

• Triple rate SDI support with automatic rate detect
• SMPTE scrambling, descrambling and framing
• Audio embedding and de-embedding
• Test pattern generation for development and validation
• 20:5 output muxing and 5:20 input demuxing to support the 5-bit LVDS interface bus
• SMBus management interface

By providing both the hardware and FPGA firmware, TI enables maximum flexibility to modify system design, quickly adapt to standard changes, add features, and reduce time-to-market. Competing solutions that integrate the protocol blocks locally in the discrete SerDes, constrain system designs to a minimal set of digital functions.

In addition to the FPGA IP provided by TI, Altera provides its own version of FPGA IP to do SMPTE SDI protocol processing. The table below compares the feature set of the different FPGA IPs. The FPGA IP provided by Altera can be downloaded from Altera's website.

TI FPGA IP

The FPGA IP is available for download as a SRAM Object File (SOF) file. Texas Instruments provides synthesizable FPGA source code in both Verilog and VHDL formats. Please contact your local TI representative to obtain a login and password to the FPGA IP FTP site.

In addition to the FPGA IP provided by TI, Altera provides its own version of FPGA IP to do SMPTE SDI protocol processing. The table below compares the feature set of the different FPGA IPs. The FPGA IP provided by Altera can be downloaded from Altera's website.

Additional SDALTEVK Design Resources

• Frequently Asked Questions (FAQ)
• Kit Photo and Description
• Layout files (please contact your local TI sales representative)

Ordering Info

• TI SDALTEVK
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